MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 302

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Transfer acknowledge
Transfer error
Signal Name
acknowledge
Burst inhibit
DATA[0:31]
Data bus
/
MPC556
TEA
TA
BI
Table 9-1 MPC555 / MPC556 SIU Signals (Continued)
Pins
32
1
1
1
EXTERNAL BUS INTERFACE
Active
LOW
High
Low
Low
Transfer Cycle Termination
Rev. 15 October 2000
I/O
Data
O
O
O
O
I
I
I
I
The data bus has the following byte lane assign-
ments:
Data Byte
DATA[0:7]
DATA[8:15]
DATA[16:23] 2
DATA[24:31] 3
Driven by the MPC555 / MPC556 when it owns the
external bus and it initiated a write transaction to a
slave device. For single beat transactions, the byte
lanes not selected for the transfer by ADDR[30:31]
and TSIZ[0:1] do not supply valid data.
In addition, the MPC555 / MPC556 drives DATA[0:31]
when an external master owns the external bus and
initiated a read transaction to an internal slave mod-
ule.
Driven by the slave in a read transaction. For single
beat transactions, the MPC555 / MPC556 does not
sample byte lanes that are not selected for the trans-
fer by ADDR[30:31] and TSIZ[0:1].
In addition, an external master that owns the bus and
initiated a write transaction to an internal slave mod-
ule drives DATA[0:31].
Driven by the slave device to which the current trans-
action was addressed. Indicates that the slave has re-
ceived the data on the write cycle or returned data on
the read cycle. If the transaction is a burst, TA should
be asserted for each one of the transaction beats.
Driven by the MPC555 / MPC556 when the slave de-
vice is controlled by the on-chip memory controller or
when an external master initiated a transaction to an
internal slave module.
Driven by the slave device to which the current trans-
action was addressed. Indicates that an error condi-
tion has occurred during the bus cycle.
Driven by the MPC555 / MPC556 when the internal
bus monitor detected an erroneous bus condition, or
when an external master initiated a transaction to an
internal slave module and an internal error was de-
tected.
Driven by the slave device to which the current trans-
action was addressed. Indicates that the current slave
does not support burst mode.
Driven by the MPC555 / MPC556 when the slave de-
vice is controlled by the on-chip memory controller.
the MPC555 / MPC556 also asserts BI for any exter-
nal master burst access to internal MPC555 /
MPC556 memory space.
0
1
Byte Lane
Description
MOTOROLA
9-6