MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 481

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SPCR3 — QSPI Control Register
SPCR2 — QSPI Control Register 2
14.7.1.4 QSPI Control Register 3
MPC555
USER’S MANUAL
RESET:
SPIFIE WREN WRTO
Bit(s)
MSB
11:15
8:10
MSB
3:7
0
0
RESET:
0
1
2
0
0
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSPI has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation.
*See bit descriptions in
1
0
/
NEWQP
ENDQP
SPIFIE
1
0
WREN
WRTO
MPC556
Name
Reserved
—
2
0
2
0
SPI finished interrupt enable. Refer to
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
Wrap enable. Refer to
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
Wrap to. When wraparound mode is enabled and after the end of queue has been reached,
WRTO determines which address the QSPI executes next. The end of queue is determined by
an address match with ENDQP.
0 = Wrap to pointer address 0x0
1 = Wrap to address in NEWQP
Ending queue pointer. This field determines the last absolute address in the queue to be com-
pleted by the QSPI. After completing each command, the QSPI compares the queue pointer val-
ue of the just-completed command with the value of ENDQP. If the two values match, the QSPI
sets SPIF to indicate it has reached the end of the programmed queue. Refer to
Operation
Reserved
New queue pointer value. This field contains the first QSPI queue address. Refer to
Operation
3
0
3
0
Table
QUEUED SERIAL MULTI-CHANNEL MODULE
4
0
Table 14-16 SPCR2 Bit Descriptions
4
0
for more information.
for more information.
14-18.
LOOP
ENDQP
Q
5
0
5
0
14.7.5.7 Master Wraparound
HMIE
Rev. 15 October 2000
6
0
6
0
HALT
7
0
7
0
14.7.4.2 QSPI
8
8
0
Description
Reserved
9
9
0
Interrupts.
Mode.
10
10
0
11
11
0
SPSR*
12
12
0
NEWQP
13
13
0
0x30 501E
0x30 501C
14.7.4 QSPI
MOTOROLA
14.7.4 QSPI
14
14
0
14-19
LSB
LSB
15
15
0