MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 167

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.15.4.2 Machine Check Interrupt
3.15.4.3 Data Storage Interrupt
MPC555
USER’S MANUAL
A machine check interrupt indication is received from the U-bus as a possible re-
sponse either to the address or data phase. It is usually caused by one of the following
conditions:
As defined in the OEA, machine check interrupts are enabled when MSR
MSR
the checkstop state. The behavior of the MPC555 / MPC556 in checkstop state is de-
pendent on the working mode as defined in
Mode
mode instead of the checkstop state. When in debug mode disable, instruction pro-
cessing is suspended and cannot be restarted without resetting the core.
An indication is sent to the SIU which may generate an automatic reset in this condi-
tion. Refer to
enabled, MSR
following registers are set.
For load/store bus cases, these registers are also set:
Execution resumes at offset 0x00200 from the base address indicated by MSR
A data storage interrupt is never generated by the hardware. The software may branch
to this location as a result of implementation-specific data storage protection error in-
terrupt.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
• The accessed address does not exist
• A data error is detected
/
ME
MPC556
Disable. When the processor is in debug mode enable, it enters the debug
= 0 and a machine check interrupt indication is received, the processor enters
Register Name
SECTION 7 RESET
ME
= 1, it is taken. If SRR1 Bit 30 = 1, the interrupt is recoverable and the
CENTRAL PROCESSING UNIT
10:15
Other
Other
Bits
ME
2:4
LE
IP
1
Rev. 15 October 2000
for more details. If the machine check interrupt is
Set to the effective address of the instruction that caused the
interrupt
Set to 1 for instruction fetch-related errors and 0 for load/
store-related errors
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
No change
No change
Bit is copied from ILE
Set to 0
21.4.1.1 Debug Mode Enable vs. Debug
RI
Description
MOTOROLA
ME
= 1. If
IP
.
3-45