MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 276

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.8.2 Power Mode Descriptions
8.8.3 Exiting from Low-Power Modes
MPC555
USER’S MANUAL
Table 8-5
for each power mode.
Exiting from low-power modes occurs through an asynchronous interrupt or a synchro-
nous interrupt generated by the memory controller. Any enabled asynchronous inter-
rupt clears the LPM bits but does not change the PLPRCR[CSRC] bit.
The exit from normal-low, doze-high, and low modes and sleep mode to normal-high
mode is accomplished with the asynchronous interrupt. The sources of the asynchro-
nous interrupt are:
The system response to asynchronous interrupts is fast. The wake-up time from nor-
mal-low, doze-high, doze-low, and sleep mode due to an asynchronous interrupt or
• Asynchronous wake-up interrupt from the interrupt controller
• RTC, PIT, or time base interrupts (if enabled)
• Decrementer exception
/
MPC556
Normal-low (“gear”)
describes the power consumption, clock frequency, and chip functionality
Operation Mode
Normal-high
Power-down
Deep-sleep
VDDSRAM
Doze-high
Doze-low
Table 8-4 Power Mode Control Bit Descriptions
Sleep
Normal-low (“gear”)
Table 8-5 Power Mode Descriptions
Power Mode
Normal-high
Power-down
Deep-sleep
Doze-high
Doze-low
Sleep
CLOCKS AND POWER CONTROL
Not active
Not active
Not active
Active
Active
Active
Active
Active
SPLL
Rev. 15 October 2000
LPM[0:1]
Full frequency ÷
Full frequency ÷
Full frequency ÷
Full frequency ÷
00
00
01
01
10
11
11
Not active
Not active
Not active
Not active
2
2
Clocks
2
2
DFNL+1
DFNL+1
DFNH
DFNH
CSRC
X
X
X
0
1
0
1
Full functions not in use
Enabled: RTC, PIT, TB
Enabled: RTC, PIT,
(RCPU, BBC, FPU)
Disabled: extended
memory controller
TEXPS
Functionality
TB and DEC,
SRAM’s data
X
X
X
X
X
1
0
are shut off
and DEC
retention
core
MOTOROLA
8-16