MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 717

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.3.3 Watchpoint Counters
21.3.3.1 Trap Enable Programming
21.4 Development System Interface
MPC555
USER’S MANUAL
There are two 16-bit watchpoint counters. Each counter is able to count one of the in-
struction watchpoints or one of the load/store watchpoints. Both generate the corre-
sponding breakpoint when they reach ZERO.
When working in the masked mode, the counters do not count watchpoints detected
when MSRRI = 0. See
The counters value when counting watchpoints programmed on the actual instructions
that alter the counters, are not predictable. Reading values from the counters when
they are active, must be synchronized by inserting a sync instruction before the actual
read is performed.
When programmed to count load/store watchpoints, the last instruction which decre-
ments the counter to ZERO is treated like any other load/store breakpoint in the sense
that it is executed and the machine branches to the breakpoint exception routine AF-
TER it executes this instruction. Therefore, the value of the counter inside the break-
point exception routine equals ZERO.
The trap enable bits can be programmed by regular software (only if MSRPR = 0) us-
ing THE mtspr instruction or “on the fly” using the special development port interface.
For more information refer to section
cations — Trap Enable
The value used by the breakpoints generation logic is the bit wise OR of the software
trap enable bits, (the bits written using the mtspr) and the development port trap en-
able bits (the bits serially shifted using the development port).
All bits, the software trap enable bits and the development port trap enable bits, can
be read from ICTRL and the LCTRL2 using mfspr. For the exact bits placement refer
to
Register 2
When debugging an existing system, it is sometimes desirable to be able to do so with-
out the need to insert any changes in the existing system. In some cases it is not de-
21.7.6 I-Bus Support Control Register
/
MPC556
When programmed to count instruction watchpoints, the last instruc-
tion which decrements the counter to ZERO is treated like any other
instruction breakpoint in the sense that it is not executed and the ma-
chine branches to the breakpoint exception routine BEFORE it exe-
cutes this instruction. As a side effect of this behavior, the value of
the counter inside the breakpoint exception routine equals ONE and
not ZERO as might be expected.
21.3.1.4 Context Dependent Filter
Mode.
DEVELOPMENT SUPPORT
Rev. 15 October 2000
21.5.6.5 Development Port Serial Communi-
NOTE
and to
21.7.8 L-Bus Support Control
MOTOROLA
21-21