MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 631

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Bit(s)
1:4
7:8
10
11
12
13
14
15
0
5
6
9
/
MPC556
Name
HOT4
CLKS
BLC
FRZ
CCL
BM
BC
BH
BP
BT
BL
—
Hang on T4
0 = Exit wait on T4 state caused by assertion of HOT4
1 = Enter wait on T4 state
Reserved
Branch latch control
0 = Latch conditions into branch condition register before exiting halted state
1 = Do not latch conditions into branch condition register before exiting the halted state or during
Stop clocks (to TCRs)
0 = Do not stop TCRs
1 = Stop TCRs during the halted state
FREEZE assertion response. The FRZ bits specify the TPU microengine response to the IMB3
FREEZE signal
00 = Ignore freeze
01 = Reserved
10 = Freeze at end of current microcycle
11 = Freeze at next time-slot boundary
Channel conditions latch. CCL controls the latching of channel conditions (MRL and TDL) when
the CHAN register is written.
0 = Only the pin state condition of the new channel is latched as a result of the write CHAN reg-
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write
µPC breakpoint enable
0 = Breakpoint not enabled
1 = Break if µPC equals µPC breakpoint register
Channel breakpoint enable
0 = Breakpoint not enabled
1 = Break if CHAN register equals channel breakpoint register at beginning of state or when
Host service breakpoint enable
0 = Breakpoint not enabled
1 = Break if host service latch is asserted at beginning of state
Link service breakpoint enable
0 = Breakpoint not enabled
1 = Break if link service latch is asserted at beginning of state
MRL breakpoint enable
0 = Breakpoint not enabled
1 = Break if MRL is asserted at beginning of state
TDL breakpoint enable
0 = Breakpoint not enabled
1 = Break if TDL is asserted at beginning of state
the time-slot transition period
ister microinstruction
CHAN register microinstruction
CHAN is changed through microcode
Table 17-7 DSCR Bit Descriptions
TIME PROCESSOR UNIT 3
Rev. 15 October 2000
Description
MOTOROLA
17-13