MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 34

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Number
16-3
16-4
16-5
16-6
17-1
17-2
17-3
17-4
18-1
18-2
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
20-1
20-2
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
22-1
22-2
22-3
22-4
22-5
MPC555 / MPC555
USER’S MANUAL
Figure
Extended ID Message Buffer Structure ........................................................ 16-4
Standard ID Message Buffer Structure ......................................................... 16-4
Interrupt levels on IRQ with ILBS ............................................................... 16-20
TouCAN Message Buffer Memory Map ...................................................... 16-22
TPU3 Block Diagram .................................................................................... 17-1
TPU3 Interrupt Levels ................................................................................... 17-5
TCR1 Prescaler Control ............................................................................... 17-7
TCR2 Prescaler Control ............................................................................... 17-8
DPTRAM Configuration ................................................................................ 18-2
DPTRAM Memory Map ................................................................................ 18-3
CMF Array and Control Register Addressing ............................................... 19-4
Shadow Information .................................................................................... 19-16
Program State Diagram .............................................................................. 19-20
Erase State Diagram .................................................................................. 19-25
Pulse Status Timing .................................................................................... 19-27
Censorship States and Transitions ............................................................. 19-35
EPEE Digital Filter and Latch ..................................................................... 19-36
CMF_EPEE Timing Diagram ...................................................................... 19-37
VPP and VDDL Power Switching ............................................................... 19-38
VPP Conditioning Circuit ............................................................................ 19-39
SRAM Block Diagram ................................................................................... 20-1
SRAM Memory Map ..................................................................................... 20-2
Watchpoints and Breakpoint Support in the CPU ....................................... 21-10
Partially Supported Watchpoint/Breakpoint Example ................................. 21-15
Instruction Support General Structure ........................................................ 21-17
Load/Store Support General Structure ....................................................... 21-20
Functional Diagram of MPC555 / MPC556 Debug Mode Support ............. 21-23
Debug Mode Logic ..................................................................................... 21-25
Debug Mode Reset Configuration .............................................................. 21-27
Asynchronous Clock Serial Communications ............................................. 21-35
Synchronous Self Clock Serial Communication ......................................... 21-36
Enabling Clock Mode Following Reset ....................................................... 21-37
Download Procedure Code Example ......................................................... 21-42
Slow Download Procedure Loop ................................................................ 21-42
Fast Download Procedure Loop ................................................................. 21-42
JTAG Pins .................................................................................................... 22-1
Test Logic Block Diagram ............................................................................. 22-2
TAP Controller State Machine ...................................................................... 22-4
Bypass Register ........................................................................................... 22-6
Output Pin Cell (O.pin) ................................................................................. 22-8
Rev. 15 October 2000
LIST OF FIGURES
MOTOROLA
Number
Page
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