MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 471

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

QSPI_IL — QSPI Interrupt Level Register
14.6 QSMCM Pin Control Registers
MPC555
USER’S MANUAL
RESET:
MSB
Bit(s)
11:15
0
0
0:10
Table 14-7
The QSMCM uses 12 pins. Eleven of the pins, when not being used by the serial sub-
systems, form a parallel port on the MCU. (The ECK pin is a dedicated external clock
source.)
The port QS pin assignment register (PQSPAR) governs the usage of QSPI pins.
Clearing a bit assigns the corresponding pin to general-purpose I/O; setting a bit as-
signs the pin to the QSPI.
PQSPAR does not affect operation of the SCI. When the SCIx transmitter is disabled,
TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete in-
put. When the SCIx transmitter or receiver is enabled, the associated TXDx or RXDx
pin is assigned its SCI function.
The port QS data direction register (DDRQS) determines whether QSPI pins are in-
puts or outputs. Clearing a bit makes the corresponding pin an input; setting a bit
makes the pin an output. DDRQS affects both QSPI function and I/O function.
14-10
/
MPC556
1
0
summarizes the effect of DDRQS bits on QSPI pin function.
ILQSPI
Name
—
lists the three QSMCM pin control registers.
2
0
0x30 5014
0x30 5016
0x30 5017
Address
3
0
Table 14-7 QSMCM Pin Control Registers
Reserved
Interrupt level of SPI
00000 = lowest interrupt level request (level 0)
11111 = highest interrupt level request (level 31)
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-6 QSPI_IL Bit Descriptions
4
0
RESERVED
QSMCM Port Data Register (PORTQS)
See
descriptions.
PORTQS Pin Assignment Register (PQSPAR)
See
PORTQS Data Direction Register (DDRQS)
See
5
0
Rev. 15 October 2000
14.6.1 Port QS Data Register (PORTQS)
Table 14-11
Table 14-11
6
0
7
0
for bit descriptions.
for bit descriptions.
Register
8
Description
9
10
11
for bit
12
ILQSPI
13
0x30 5006
MOTOROLA
14
Table
LSB
14-9
15