MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 453

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

QASR0 — QADC64 Status Register
RESET:
MPC555
USER’S MANUAL
Bit(s)
MSB
CF1
0
0
0
1
2
3
4
5
The four flag bits and the two trigger overrun bits are cleared by writing a zero to the
bit after the bit was previously read as a one.
PF1
/
1
0
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Name
TOR1
TOR2
CF1
CF2
PF1
PF2
CF2
2
0
Queue 1 completion flag. CF1 indicates that a queue 1 scan has been completed. CF1 is set by
the QADC64 when the conversion is complete for the last CCW in queue 1, and the result is
stored in the result table.
0 = Queue 1 scan is not complete
1 = Queue 1 scan is complete
Queue 1 pause flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the
QADC64 when the current queue 1 CCW has the pause bit set, the selected input channel has
been converted, and the result has been stored in the result table.
0 = Queue 1 has not reached a pause
1 = Queue 1 has reached a pause
Queue 2 completion flag. CF2 indicates that a queue 2 scan has been completed. CF2 is set by
the QADC64 when the conversion is complete for the last CCW in queue 2, and the result is
stored in the result table.
0 = Queue 2 scan is not complete
1 = Queue 2 scan is complete
Queue 2 pause flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the
QADC64 when the current queue 2 CCW has the pause bit set, the selected input channel has
been converted, and the result has been stored in the result table.
0 = Queue 2 has not reached a pause
1 = Queue 2 has reached a pause
— Queue 1 trigger overrun. TOR1 indicates that an unexpected queue 1 trigger event has oc-
curred. TOR1 can be set only while queue 1 is active.
A trigger event generated by a transition on ETRIG1/ETRIG2 may be recorded as a trigger over-
run. TOR1 can only be set when using an external trigger mode. TOR1 cannot occur when the
software initiated single-scan mode or the software initiated continuous-scan mode is selected.
0 = No unexpected queue 1 trigger events have occurred
1 = At least one unexpected queue 1 trigger event has occurred
Queue 2 trigger overrun. TOR2 indicates that an unexpected queue 2 trigger event has occurred.
TOR2 can be set when queue 2 is in the active, suspended, and trigger pending states.
A trigger event generated by a transition depending on the value of TRG in QACR or ETRIG1/
ETRIG2 or by the periodic/interval timer may be recorded as a trigger overrun. TOR2 can only
be set when using an external trigger mode or a periodic/interval timer mode. Trigger overruns
cannot occur when the software initiated single-scan mode and the software initiated continuous-
scan mode are selected.
0 = No unexpected queue 2 trigger events have occurred
1 = At least one unexpected queue 2 trigger event has occurred
PF2
3
0
TOR1 TOR2
Table 13-16 QASR0 Bit Descriptions
4
0
5
0
Rev. 15 October 2000
6
0
7
0
QS
8
0
Description
9
0
10
0
11
0
12
0
CWP
13
0
0x30 4C10
0x30 4810
MOTOROLA
14
0
13-41
LSB
15
0