MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 75

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.3.1.21 WE[0:3]/BE[0:3]/AT[0:3]
2.3.1.22 PORESET
2.3.1.23 HRESET
2.3.1.24 SRESET
2.3.1.25 SGPIOC[6]/FRZ/PTR
MPC555
USER’S MANUAL
Pin Name: we_b_at[0:3](4 pins)
Write Enable[0:3]/Byte Enable[0:3] – This output line is asserted when a write ac-
cess to an external slave controlled by the GPCM in the memory controller is initiated
by the chip. It can be optionally be asserted on all read and write accesses. See WEBS
bit definition in
valid data to be stored by the slave device. WE[1]/BE[1] is asserted if the data lane
DATA[8:15] contains valid data to be stored by the slave device. WE[2]/BE[2] is as-
serted if the data line DATA[16:23] contains valid data to be stored by the slave device.
WE[3]/BE[3] is asserted if the data lane DATA[24:31] contains valid data to be stored
by the slave device.
Address Type – Indicates one of the 16 address types to which the address applies.
The address type signals are valid at the rising edge of the clock in which the Special
Transfer Start (STS) is asserted.
Pin Name: poreset_b
Power on Reset – This pin should be activated as a result of a voltage failure on the
keep-alive power pins. The pin has a glitch detector to ensure that low spikes of less
than 20 ns are rejected. The internal PORESET signal is asserted only if PORESET
is asserted for more than 100 ns. See
Pin Name: hreset_b
Hard Reset – The chip can detect an external assertion of HRESET only if it occurs
while the chip is not asserting reset. After negation of HRESET or SRESET is detect-
ed, a 16 cycles period is taken before testing the presence of an external reset. The
internal HRESET signal is asserted only if HRESET is asserted for more than 100 ns.
To meet external timing requirements, an external pull-up device is required to negate
HRESET. See
Pin Name: sreset_b
Soft Reset – The chip can detect an external assertion of SRESET only if it occurs
while the chip is not asserting reset. After negation of HRESET or SRESET is detect-
ed, a 16-cycle period is taken before testing the presence of an external soft reset. To
meet external timing requirements, an external pull-up device is required to negate
SRESET. See
Pin Name: sgpioc6_frz_ptr_b
/
MPC556
Table
SECTION 7 RESET
SECTION 7 RESET
10-7. WE[0]
SIGNAL DESCRIPTIONS
Rev. 15 October 2000
/
BE[0] is asserted if the data lane DATA[0:7] contains
for more details on timing.
for more details on timing.
SECTION 7 RESET
for more details on timing.
MOTOROLA
2-17