MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 725

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.4.1.3 The Check Stop State and Debug Mode
21.4.1.4 Saving Machine State upon Entering Debug Mode
MPC555
USER’S MANUAL
NOTES:
MSR
The processor enters into the debug mode state when at least one of the bits in the
exception cause register (ECR) is set, the corresponding bit in the debug enable reg-
ister (DER) is enabled and debug mode is enabled. When debug mode is enabled and
an enabled event occurs, the processor waits until its pipeline is empty and then starts
fetching the next instructions from the development port. For information on the exact
value of machine status save/restore registers (SRR0 and SRR1) refer to
terrupts
When the processor is in debug mode the freeze indication is asserted thus allowing
any peripheral that is programmed to do so to stop. The fact that the CPU is in debug
mode is also broadcast to the external world using the value b11 on the VFLS pins.
The development port should read the value of the exception cause register (ECR) in
order to get the cause of the debug mode entry. Reading the exception cause register
(ECR) clears all its bits.
The CPU enters the check stop state if the machine check interrupt is disabled
(MSRME = 0) and a machine check interrupt is detected. However, if a machine check
interrupt is detected when MSRME = 0, debug mode is enabled and the check stop
enable bit in the debug enable register (DER) is set, the CPU enters debug mode rath-
er then the check stop state.
The different actions taken by the CPU when a machine check interrupt is detected
are shown in the following table.
If entering debug mode was as a result of any load/store type exception, and therefore
the DAR (data address register) and DSISR (data storage interrupt status register)
1. Check stop enable bit in the debug enable register (DER)
2. Machine check interrupt enable bit in the debug enable register (DER)
0
1
0
0
1
1
ME
/
MPC556
Enable
Debug
Mode
The freeze signal can be asserted by software when debug mode is
disabled.
0
0
1
1
1
1
Table 21-9 The Check Stop State and Debug Mode
CHSTPE
X
X
X
X
0
1
1
DEVELOPMENT SUPPORT
Rev. 15 October 2000
MCIE
X
X
X
X
0
1
2
Detecting a Machine Check Interrupt
Enter the check stop state
Branch to the machine check interrupt
Enter the check stop state
Enter Debug Mode
Branch to the machine check interrupt
Enter Debug Mode
Action Performed by the CPU when
NOTE
Exception Cause
Register (ECR)
0x20000000
0x10000000
0x20000000
0x20000000
0x10000000
0x10000000
MOTOROLA
Value
3.15.4 In-
21-29