MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 522

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Bit(s)
12:15
0:3
10
11
4
5
6
7
8
9
/
QTPNT
QBHFI
QTHEI
QBHEI
QTHFI
QTWE
MPC556
Name
QTSZ
QRE
QTE
—
Queue transmit pointer. QTPNT is a 4-bit counter used to indicate the next data frame within the
transmit queue to be loaded into the SC1DR. This feature allows for ease of testability. This field
is writable in test mode only; otherwise it is read-only.
Receiver queue top-half full interrupt. When set, QTHFI enables an SCI1 interrupt whenever the
QTHF flag in QSCI1SR is set. The interrupt is blocked by negating QTHFI. This bit refers to the
queue locations SCRQ[0:7].
0 = QTHF interrupt inhibited
1 = Queue top-half full (QTHF) interrupt enabled
Receiver queue bottom-half full interrupt. When set, QBHFI enables an SCI1 interrupt whenever
the QBHF flag in QSCI1SR is set. The interrupt is blocked by negating QBHFI. This bit refers to
the queue locations SCRQ[8:15].
0 = QBHF interrupt inhibited
1 = Queue bottom-half full (QBHF) interrupt enabled
Transmitter queue top-half empty interrupt. When set, QTHEI enables an SCI1 interrupt when-
ever the QTHE flag in QSCI1SR is set. The interrupt is blocked by negating QTHEI. This bit refers
to the queue locations SCTQ[0:7].
0 = QTHE interrupt inhibited
1 = Queue top-half empty (QTHE) interrupt enabled
Transmitter queue bottom-half empty interrupt. When set, QBHEI enables an SCI1 interrupt
whenever the QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This
bit refers to the queue locations SCTQ[8:15].
0 = QBHE interrupt inhibited
1 = Queue bottom-half empty (QBHE) interrupt enabled
Reserved
Queue transmit enable. When set, the transmit queue is enabled and the TDRE bit should be
ignored by software. The TC bit is redefined to indicate when the entire queue is finished trans-
mitting. When clear, the SCI1 functions as described in the previous sections and the bits related
to the queue (Section 5.5 and its subsections) should be ignored by software with the exception
of QTE.
0 = Transmit queue is disabled
1 = Transmit queue is enabled
Queue receive enable. When set, the receive queue is enabled and the RDRF bit should be ig-
nored by software. When clear, the SCI1 functions as described in the previous sections and the
bits related to the queue (Section 5.5 and its subsections) should be ignored by software with the
exception of QRE.
0 = Receive queue is disabled
1 = Receive queue is enabled
Queue transmit wrap enable. When set, the transmit queue is allowed to restart transmitting from
the top of the queue after reaching the bottom of the queue. After each wrap of the queue, QTWE
is cleared by hardware.
0 = Transmit queue wrap feature is disabled
1 = Transmit queue wrap feature is enabled
Queue transfer size. The QTSZ bits allow programming the number of data frames to be trans-
mitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified. QTSZ is
loaded into QPEND initially or when a wrap occurs.
Table 14-30 QSCI1CR Bit Descriptions
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
Description
MOTOROLA
14-60