MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 439

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Figure 13-8
erator. A 5-bit down counter, clocked at the IMB clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of the QCLK.
The PSA bit was maintained for software compatibility, but has no effect on QADC64.
The following equations define QCLK frequency:
The following are equations for calculating the QCLK high/low phases in Example 1:
The following are equations for calculating the QCLK high/low phases in Example 2:
Where:
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
• PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
• PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
• F
• FQCLK = QCLK frequency
SYS
The guideline for selecting PSH and PSL is select is to maintain ap-
proximately 50% duty cycle. So for prescaler values less then 16, or
PSH ~= PSL. For prescaler values greater than 16 keep PSL as large
as possible.
shows that the prescaler is essentially a variable pulse width signal gen-
= IMB clock frequency
FQCLK= 1 ÷ (High QCLK Time + Low QCLK Time)
High QCLK Time = (11 + 1) ÷ 40 x 10
High QCLK Time = (7 + 1) ÷ 32 x 10
Low QCLK Time = (7 + 1) ÷ 40 x 10
Low QCLK Time = (7 + 1) ÷ 32 x 10
High QCLK Time = (PSH + 1) ÷ F
Low QCLK Time = (PSL + 1) ÷ F
FQCLK = 1/(300 + 200) = 2 MHz
Rev. 15 October 2000
NOTE
6
6
6
6
= 200 ns
= 250 ns
SYS
= 250 ns
SYS
= 300 ns
MOTOROLA
13-27