MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 166

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.15.3 Storage Control Instructions
3.15.4 Interrupts
3.15.4.1 System Reset Interrupt
MPC555
USER’S MANUAL
Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlb-
sync are not implemented by the MPC555 / MPC556.
The core implements all storage-associated interrupts as precise interrupts. This
means that a load/store instruction is not complete until all possible error indications
have been sampled from the load/store bus. This also implies that a store, or a non-
speculative load instruction is not issued to the load/store bus until all previous instruc-
tions have completed. In case of a late error, a store cycle (or a nonspeculative load
cycle) can be issued and then aborted.
In each interrupt handler, when registers SRR0 and SRR1 are saved, MSR
set to 1.
The following paragraphs define the types of OEA interrupts The exception table vec-
tor defines the offset value by interrupt type. Refer to
A system reset interrupt occurs when the IRQ0 pin is asserted and the following reg-
isters are set.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
• Added Registers — For a list of added special purpose registers, refer to
/
DBAT3U, DBAT3L
3-2, and
MPC556
Register Name
Table
3-3.
CENTRAL PROCESSING UNIT
10:15
Other
Other
Bits
ME
1:4
LE
IP
Rev. 15 October 2000
Set to the effective address of the instruction that the proces-
sor attempts to execute next if no interrupt conditions are
present
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
No change
No change
Bit is copied from ILE
Set to 0
RI
Description
Table
3-21.
MOTOROLA
RI
can be
Table
3-44