MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 815

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
D.1 Overview
MPC555 / MPC556
USER’S MANUAL
The following pages provide brief descriptions of the pre-programmed functions in the
TPU3. For detailed descriptions, refer to the programming note for the individual func-
tion. The Motorola
programming notes.
The TPU3 contains four Kbytes of microcode ROM. This appendix defines the func-
tions that are in the standard ROM on the MPC555 / MPC556. The TPU3 can have up
to eight Kbytes of memory and a maximum of four entry tables (see
The TPU3 can address up to eight Kbytes of memory at any one time. It has four
Kbytes of internal ROM, located in Bank 0 and Bank 1, and six Kbytes of dual-ported
SRAM (DPTRAM), located in Bank 0, Bank 1and Bank 2. As only one type of memory
can be used at a time, the TPU3 must either use the internal ROM or the SRAM. Func-
tions from both memory types cannot be used in conjunction.
*The DPTRAM is located at 0x30 2000 until it is switched to emulation mode.
In emulation mode, the DPTRAM is accessible by the TPUs only.
Add - Entry
Add - Entry
Add - Entry
TPUROM
Code
Code
Entry
Code
Code
TPU Literature Pack,
Figure D-1 TPU3 Memory Map
TPU ROM FUNCTIONS
7FF
0
1FF
3 FF
TPU ROM FUNCTIONS
Rev. 15 October 2000
APPENDIX D
TPULITPAK/D, provides a list of available
Add - Entry
Add - Entry
DPTRAM*
Code
Entry
Code
Code
1FF
3FF
5 FF
0
Figure
MOTOROLA
D-1).
D-1

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