MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 467

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Access
14.5.1 Low-Power Stop Operation
14.5.2 Freeze Operation
14.5.3 Access Protection
MPC555
USER’S MANUAL
NOTES:
1. S = Supervisor access only
2. 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
S
T
S
S
When the STOP bit in QSMCMMCR is set, the IMB clock input to the QSMCM is dis-
abled and the module enters a low-power operating state. QSMCMMCR is the only
register guaranteed to be readable while STOP is asserted. The QSPI RAM is not
readable in low-power stop mode. However, writes to RAM or any register are guar-
anteed valid while STOP is asserted. STOP can be written by the CPU and is cleared
by reset.
System software must bring each submodule to an orderly stop before setting STOP
to avoid data corruption. The SCI receiver and transmitter should be disabled after
transfers in progress are complete. The QSPI can be halted by setting the HALT bit in
SPCR3 and then setting STOP after the HALTA flag is set.
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3
FREEZE signal is asserted. FREEZE is asserted when the CPU enters background
debug mode. Setting FRZ1 causes the QSPI to halt on the first transfer boundary fol-
lowing FREEZE assertion. FREEZE causes the SCI1 transmit queue to halt on the first
transfer boundary following FREEZE assertion.
The SUPV bit in the QMCR defines the assignable QSMCM registers as either super-
visor-only data space or unrestricted data space.
When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only
space. For any access from within user mode, the IMB3 address acknowledge (AACK)
signal is asserted and a bus error is generated.
Because the QSMCM contains a mix of supervisor and user registers, AACK is assert-
ed for either supervisor or user mode accesses, and the bus cycle remains internal. If
a supervisor-only register is accessed in user mode, the module responds as if an ac-
cess had been made to an unauthorized register location, and a bus error is generat-
ed.
S/U = Supervisor access only or unrestricted user access (assignable data space).
1
/
0x30 5000
0x30 5002
0x30 5004
0x30 5006
MPC556
Address
MSB
Dual SCI Interrupt Level (QDSCI_IL)
2
See
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-2 QSMCM Global Registers
Table 14-5
Reserved
QSMCM Module Configuration Register (QSMCMMCR)
Rev. 15 October 2000
for bit descriptions.
See
QSMCM Test Register (QTEST)
Table 14-4
for bit descriptions.
Queued SPI Interrupt Level (QSPI_IL)
See
Table 14-6
Reserved
for bit descriptions.
MOTOROLA
14-5
LSB