MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 549

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.9.1.1 MCPSM Status/Control Register (MCPSMCSCR)
MCPSMSCR — MCPSM Status/Control Register
15.10 MIOS Modulus Counter Submodule (MMCSM)
MPC555
USER’S MANUAL
PREN FREN
MSB
Bit(s)
12:15
2:11
0
0
RESET:
0
1
This register contains status and control information for the MCPSM.
The MMCSM is a versatile counter submodule capable of performing complex count-
ing and timing functions, including modulus counting, in a wide range of applications.
The MMCSM may also be configured as an event counter, allowing the overflow flag
to be set after a predefined number of events (internal clocks or external events), or
1
0
/
MPC556
Name
PREN
FREN
PSL
—
0x30 6810 –
0x30 6814
0x30 6816
2
0
Address
Prescaler enable. This active high read/write control bit enables the MCPSM counter. The PREN
bit is cleared by reset.
0 = MCPSM counter disabled.
1 = MCPSM counter enabled.
Freeze enable. This active high read/write control bit when set make possible a freeze of the
MCPSM counter if the MIOB freeze line is activated. Note that this line is active when the
MIOS1MCR STOP bit is set or when the MIOS1MCR FREN bit and the IMB3 FREEZE line are
set.
When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the
freeze condition on the MIOB is negated, the counter restarts from where it was before being
frozen. The FREN bit is cleared by reset.
0 = MCPSM counter not frozen.
1 = Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3.
Reserved
Clock prescaler. This 4-bit read/write data register stores the modulus value for loading into the
clock prescaler. The new value is loaded into the counter on the next time the counter equals
one or when disabled (PREN bit = 0). Divide ratios are as follows:
0000 = 16
0001 = No counter clock output
0010 = 2
0011 = 3
.
.
.
1110 = 14
1111 = 15
3
0
Table 15-10 MCPSMSCR Bit Descriptions
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Reserved
MCPSM Status/Control Register (MCPSMSCR)
See
4
0
Table 15-10
Table 15-9 MCPSM Address Map
5
0
Rev. 15 October 2000
RESERVED
6
0
for bit descriptions.
7
0
Register
8
0
Description
9
0
10
0
11
0
12
0
13
0
PSL
0x30 6816
MOTOROLA
14
0
15-13
LSB
15
0