MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 546

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.8.2 MBISM Interrupt Registers
15.8.2.1 MIOS1 Interrupt Level Register 0 (MIOS1LVL0)
MPC555
USER’S MANUAL
Bit(s)
9:15
4:7
0
1
2
3
8
Table 15-6
This register contains the interrupt level that applies to the submodules number 15 to
zero.
/
MPC556
Name
STOP
SUPV
FRZ
RST
—
—
—
0x30 6C30
0x30 6C70
Address
shows the MBISM interrupt registers.
Table 15-6 MBISM Interrupt Registers Address Map
Stop enable. Setting the STOP bit activates the MIOB freeze signal regardless of the state of
the IMB3 FREEZE signal. The MIOB freeze signal is further validated in some submodules with
internal freeze enable bits in order for the submodule to be stopped. The MBISM continues to
operate to allow the CPU access to the submodule’s registers. The MIOB freeze signal remains
active until reset or until the STOP bit is written to zero by the CPU (via the IMB3). The STOP
bit is cleared by reset.
0 = Enables MIOS1 operation.
1 = Selectively stops MIOS1 operation.
Reserved
Freeze enable. Setting the FRZ bit, activates the MIOB freeze signal only when the IMB3
FREEZE signal is active. The MIOB freeze signal is further validated in some submodules with
internal freeze enable bits in order for the submodule to be frozen. The MBISM continues to op-
erate to allow the CPU access to the submodule’s registers. The MIOB freeze signal remains
active until the FRZ bit is written to zero or the IMB3 FREEZE signal is negated. The FRZ bit is
cleared by reset.
0 = Ignores the FREEZE signal on the IMB3, allowing MIOS1 operation.
1 = Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3.
Module reset. The RST bit always returns 0 when read and can be written to 1. When the RST
bit is written to 1, the MBISM activates the reset signal on the MIOB. This completely stops the
operation of the MIOS1 and resets all the values in the submodules registers that are affected
by reset. This bit provides a way of resetting the complete MIOS1 module regardless of the reset
state of the CPU. The RST bit is cleared by reset.
0 = Writing a 0 to RST has no effect.
1 = Reset the MIOS1 submodules
Reserved
Supervisor data space selector. The SUPV bit specifies whether the address space from 0x0000
to 0x07FF in the MIOS1 is accessed at the supervisor privilege level. When SUPV is cleared,
these addresses are accessed at the Unrestricted privilege level. The SUPV bit is cleared by
reset.
0 = Unrestricted data space.
1 = Supervisor data space.
Reserved. In implementations that use hardware interrupt arbitration, bits 12:15 represent the
IARB field.
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
MIOS1 Interrupt Level Register 0 (MIOS1LVL0)
See
MIOS1 Interrupt Level Register 1 (MIOS1LVL1)
See
Table 15-5 MIOS1MCR Bit Descriptions
Table 15-7
Table 15-8
Rev. 15 October 2000
for bit descriptions.
for bit descriptions.
Register
Description
MOTOROLA
15-10