MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 517

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
in the serial data stream, which makes SCIx tolerant to small frequency variations in
the received data stream.
The sequence of events used by the receiver to find a start bit is listed below.
Upon detection of a valid start bit, synchronization is established and is maintained
through the reception of the last stop bit, after which the procedure starts all over again
to search for a new valid start bit. During a frame's reception, SCIx resynchronizes the
RT clock on any one-to-zero transitions.
Additional logic in the receiver bit processor determines the logic level of the re-ceived
bit and implements an advanced noise-detection function. During each bit-time of a
frame (including the start and stop bits), three logic-sense samples are taken at RT8,
RT9, and RT10. The logic sense of the bit-time is decided by a majority vote of these
three samples. This logic level is shifted into register RDRx for every bit except the
start and stop bits.
If RT8, RT9, and RT10 do not all agree, an internal working noise flag is set. Addition-
ally for the start bit, if RT3, RT5, and RT7 do not all agree, the internal working noise
flag is set. If this flag is set for any of the bit-times in a frame, the NF flag in SCxSR is
set concurrently with the RDRF flag in SCxSR when the data is transferred to register
RDRx. The user must determine if the data received with NF set is valid. Noise on the
RXDx pin does not necessarily corrupt all data.
The operation of the receiver bit processor is shown in
demonstrates the search for a valid start bit and the synchronization procedure as out-
lined above. The possibilities of noise durations greater than one bit-time are not con-
sidered in this examples.
1. Sample RXDx input during each RT period and maintain these samples in a se-
2. If RXDx is low during this RT period, go to step 1.
3. If RXDx is high during this RT period, store sample and proceed to step 4.
4. If RXDx is low during this RT period, but not high for the previous three RT pe-
5. If RXDx is low during this RT period and has been high for the previous three
6. Skip RT2 but place RT3 in the pipeline and proceed to step 7.
7. Skip RT4 and sample RT5. If both RT3 and RT5 are high (RT1 was noise only),
8. Skip RT6 and sample RT7. If any two of RT3, RT5, or RT7 is high (RT1 was
9. A valid start bit is found and synchronization is achieved. From this point on until
/
MPC556
rial pipeline that is three RT periods deep.
riods (which is noise only), set an internal working noise flag and go to step 1,
since this transition was not a valid start bit transition.
RT periods, call this period RT1, set RAF, and proceed to step 6.
set an internal working noise flag. Go to step 3 and clear RAF. Otherwise, place
RT5 in the pipeline and proceed to step 8.
noise only), set an internal working noise flag. Go to step 3 and clear RAF. Oth-
erwise, place RT7 in the pipeline and proceed to step 9.
the end of the frame, the RT clock will increment starting over again with RT1
on each one-to-zero transition or each RT16. The beginning of a bit-time is thus
defined as RT1 and the end of a bit-time as RT16.
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
Figure
14-14. This example
MOTOROLA
14-55