MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 569

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers
MPC555
USER’S MANUAL
Within the MIOS1, each MIRSM includes:
One bit position in each of the above registers is associated with one submodule. Note
that if a submodule in a group of 16 cannot generate interrupts, then its corresponding
flag bit in the status register is inactive and reads as zero.
When an event occurs in a submodule that activates a flag line, the corresponding flag
bit in the status register is set. The status register is read/write, but a flag bit can be
reset only if it has previously been read as a one. Writing a one to a flag bit has no
effect. When the software intends to clear only one flag bit within a status register, the
software must write an 16-bit value of all ones except for a zero in the bit position to
be cleared.
The enable register is initialized by the software to indicate whether each interrupt re-
quest is enabled for the level defined in the ICS.
Each bit in the IRQ pending register is the result of a logical “AND” between the corre-
sponding bits in the status and in the enable registers. If a flag bit is set and the level
enable bit is also set, then the IRQ pending bit is set and the information is transferred
to the interrupt control section that is in charge of sending the corresponding level to
the CPU. The IRQ pending register is read only.
The submodule number of an interrupting source defines the corresponding MIRSM
number and the bit position in the status registers. To find the MIRSM number and bit
position of an interrupting source, divide the interrupting submodule number by 16.
The integer result of the division gives the MIRSM number. The remainder of the divi-
sion gives the bit position.
Refer to
15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers
about the registers in the MIRSM.
Table 15-28
• One 16-bit status register (for the flags)
• One 16-bit enable register
• One 16-bit IRQ pending register
/
MPC556
15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers
When the enable bit is not set for a particular submodule, the corre-
sponding status register bit is still set when the corresponding flag is
set. This allows the traditional software approach of polling the flag
bits to see which ones are set. The status register makes flag polling
easy, since up to sixteen flag bits are contained in one register.
shows the registers associated with the MIRSM0 submodule.
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Rev. 15 October 2000
NOTE
MOTOROLA
for details
and to
15-33