MPC555CME Freescale Semiconductor, MPC555CME Datasheet
MPC555CME
Specifications of MPC555CME
Related parts for MPC555CME
MPC555CME Summary of contents
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MPC555 / MPC556 USER’S MANUAL Revised 15 October 2000 Copyright 2000 MOTOROLA; All Rights Reserved ...
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MPC555 / MPC556 USER’S MANUAL Revised 15 October 2000 Copyright 2000 MOTOROLA; All Rights Reserved ...
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Paragraph Number 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 2.3.1.16 TEA ...
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Paragraph Number 2.3.3.6 VFLS[0:1]/MPIO32B[3: ...
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Paragraph Number 2.4.6.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 3.3 Instruction Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 3.11.5 Exception Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 3.15.4.2 Machine Check Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 4.6 Burst Buffer Programming Model ...
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Paragraph Number 6.13.3.1 System Protection Control Register (SYPCR 6-26 6.13.3.2 Software Service Register ...
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Paragraph Number 8.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 8.12.3 Change of Lock Interrupt Register (COLIR ...
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Paragraph Number 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 11.6.2 L2U Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 13.3.4 Multiplexed Address Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 13.12.6 QADC64 Control Register 0 (QACR0 ...
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Paragraph Number 14.7.5.1 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 14.9.12 Example QSCI1 Receive Operation of 17 Data Frames . . . . . . . . . . . . . . . . . . . . . 14-73 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) 15.1 MIOS1 Features. ...
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Paragraph Number 15.12.1.3 MPWMSM Counter Register (MPWMSMCNTR 15-28 15.12.1.4 MPWMSM Status/Control Register(MPWMSMCR ...
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Paragraph Number 16.4.2 TouCAN Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 17.3.2 Channel Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 18.4.4 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 19.8.2 Censored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Paragraph Number 21.3.1.5 Ignore First Match ...
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Paragraph Number 21.7.6 I-Bus Support Control Register ...
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Paragraph Number D.10 Multichannel Pulse-Width Modulation (MCPWM ...
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Paragraph Number G.7 DC Electrical Characteristics ...
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Figure Number 1-1 MPC555 / MPC556 Block Diagram ................................................................ 1-2 1-2 MPC555 / MPC556 Memory Map ................................................................... 1-6 1-3 MPC555 / MPC556 Internal Memory Map ...................................................... 1-7 2-1 MPC555 / MPC556 Case Dimensions and Packaging ................................... 2-2 2-2 MPC555 / ...
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Figure Number 4-8 Examples of Instruction Layout in Memory ..................................................... 4-9 4-9 Generating Compressed Code Address for PowerPC Direct Branches ................................................................... 4-10 4-10 Extracting Direct Branch Target Address in the Decompressor ................... 4-11 4-11 Code Compression Process (Phase A) ........................................................ ...
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Figure Number 9-1 Input Sample Window ..................................................................................... 9-2 9-2 MPC555 / MPC556 Bus Signals ..................................................................... 9-3 9-3 Basic Transfer Protocol .................................................................................. 9-8 9-4 Basic Flow Diagram of a Single Beat Read Cycle .......................................... 9-9 9-5 Single Beat Read Cycle–Basic Timing–Zero ...
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Figure Number 10-1 Memory Controller Function Within the USIU ............................................... 10-1 10-2 Memory Controller Block Diagram ................................................................ 10-2 10-3 MPC555 / MPC556 Simple System Configuration ....................................... 10-3 10-4 Bank Base Address and Match Structure ..................................................... 10-4 10-5 MPC555 / MPC556 ...
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Figure Number 13-7 QADC64 Queue Operation with Pause ...................................................... 13-16 13-8 QADC64 Clock Subsystem Functions ........................................................ 13-26 13-9 QADC64 Clock Programmability Examples ............................................... 13-28 13-10 QADC64 Interrupt Flow Diagram ................................................................ 13-30 13-11 Interrupt Levels on IRQ with ILBS .............................................................. 13-31 ...
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Figure Number 16-3 Extended ID Message Buffer Structure ........................................................ 16-4 16-4 Standard ID Message Buffer Structure ......................................................... 16-4 16-5 Interrupt levels on IRQ with ILBS ............................................................... 16-20 16-6 TouCAN Message Buffer Memory Map ...................................................... 16-22 17-1 TPU3 Block Diagram .................................................................................... ...
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Figure Number 22-6 Observe-Only Input Pin Cell (I.Obs) ............................................................. 22-8 22-7 Output Control Cell (IO.CTL) ........................................................................ 22-9 22-8 General Arrangement of Bidirectional Pin Cells ........................................... 22-9 D-1 TPU3 Memory Map ........................................................................................D-1 D-2 PTA Parameters .............................................................................................D-5 D-3 QOM Parameters ...........................................................................................D-7 D-4 ...
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Figure Number E-7 LC Filter Example (Alternative) ...................................................................... E-7 E-8 PLL Off-Chip Capacitor Example ................................................................... E-7 G-1 CLKOUT Timing .......................................................................................... G-16 G-2 External Clock Timing ................................................................................. G-23 G-3 Synchronous Output Signals Timing ........................................................... G-24 G-4 Synchronous Active Pull-Up and Open ...
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Figure Number Timing Diagram ........................................................................................... G-63 G-40 MMCSM Clock Pin to Counter Bus Increment Timing Diagram ........................................................................................... G-63 G-41 MMCSM Load Pin to Counter Bus Reload Timing Diagram ....................... G-63 G-42 MMCSM Counter Bus Reload to Interrupt Flag Setting Timing ...
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Figure Number MPC555 / MPC555 USER’S MANUAL LIST OF FIGURES Rev. 15 October 2000 Page Number MOTOROLA xxxviii ...
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Table Number 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA ........................................... 2-4 2-2 Pin Functionality Table .......................................................................................... 2-7 2-3 PDMCR Bit Descriptions..................................................................................... 2-29 2-4 Pin Reset State.................................................................................................... 2-32 2-5 Pad Groups Based on 3-V / 5-V Select ............................................................... 2-57 ...
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Table Number 6-1 USIU Pins Multiplexing Control.............................................................................. 6-3 6-2 SGPIO Configuration ............................................................................................. 6-7 6-3 Priority of Interrupt Sources ................................................................................. 6-12 6-4 Decrementer Time-Out Periods........................................................................... 6-13 6-5 SIUMCR Bit Descriptions.................................................................................... 6-19 6-6 Debug Pins Configuration.................................................................................... 6-20 6-7 Debug Port Pins Configuration ...
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Table Number 9-3 Data Bus Contents for Write Cycles .................................................................... 9-30 9-4 Priority Between Internal and External Masters over External Bus ..................... 9-34 9-5 Burst Length and Order ....................................................................................... 9-36 9-6 BURST/TSIZE Encoding ..................................................................................... 9-37 9-7 Address Type Pins............................................................................................... 9-37 ...
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Table Number 13-9 PORTQA, PORTQB Bit Descriptions ............................................................. 13-34 13-10 DDRQA Bit Descriptions............................................................................... 13-35 13-11 QACR0 Bit Descriptions ............................................................................... 13-36 13-12 QACR1 Bit Descriptions ............................................................................... 13-37 13-13 Queue 1 Operating Modes ............................................................................ 13-38 13-14 QACR2 Bit Descriptions ............................................................................... 13-39 13-15 ...
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Table Number 15-2 MBISM Address Map......................................................................................... 15-8 15-3 MIOS1TPCR Bit Descriptions............................................................................ 15-9 15-4 MIOS1VNR Bit Descriptions .............................................................................. 15-9 15-5 MIOS1MCR Bit Descriptions ........................................................................... 15-10 15-6 MBISM Interrupt Registers Address Map ........................................................ 15-10 15-7 MIOS1LVL0 Bit Descriptions ........................................................................... 15-11 15-8 MIOS1LVL1 ...
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Table Number 16-10 TouCAN Register Map................................................................................... 16-21 16-11 TCNMCR Bit Descriptions ............................................................................ 16-23 16-12 CANICR Bit Descriptions .............................................................................. 16-25 16-13 CANCTRL0 Bit Descriptions......................................................................... 16-25 16-14 RX MODE[1:0] Configuration......................................................................... 16-26 16-15 Transmit Pin Configuration ............................................................................ 16-26 16-16 CANCTRL1 Bit Descriptions.......................................................................... 16-27 ...
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Table Number 19-3 CMFTST Bit Descriptions .................................................................................. 19-8 19-4 CMF Programming Algorithm (v6 and Later)..................................................... 19-8 19-5 CMF Erase Algorithm (v6) ................................................................................. 19-9 19-6 CMFCTL Bit Descriptions ................................................................................ 19-10 19-7 EEPROM Array Addressing............................................................................. 19-12 19-8 CMF EEPROM Array Address Fields ...
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Table Number 22-1 JTAG Interface Pin Descriptions........................................................................ 22-3 22-2 Instruction Decoding .......................................................................................... 22-5 22-3 Boundary Scan Bit Definition ........................................................................... 22-10 A-1 SPR (Special Purpose Registers) ......................................................................... A-2 A-2 CMF (CDR MoneT Flash EEPROM) Flash Array ................................................. A-4 A-3 USIU (Unified ...
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Table Number G-17 QSPI Timing..................................................................................................... G-53 G-18 GPIO Timing .................................................................................................... G-57 G-19 TPU3 Timing .................................................................................................... G-57 G-20 TouCAN Timing ............................................................................................... G-58 G-21 MCPSM Timing Characteristics ....................................................................... G-59 G-22 MPWMSM Timing Characteristics ................................................................... G-60 G-23 MMCSM Timing Characteristics ...................................................................... G-62 G-24 ...
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Table Number MPC555 / MPC556 USER’S MANUAL LIST OF TABLES Rev. 15 October 2000 Page Number MOTOROLA xlviii ...
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This manual defines the functionality of the MPC555 / MPC556 for use by software and hardware developers. The MPC555 / MPC556 is based on the PowerPC proces- sor used in the Motorola MPC500 family of microcontrollers. For further information refer ...
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In certain contexts, such as a signal encoding, this indicates a don’t care. For example field is binary encoded 0bx001, the state of the first bit is a don’t care. Throughout this manual references ...
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The MPC555 / MPC556 is a member of Motorola’s MPC500 PowerPC controller family. The MPC555 / MPC556 offers the following features: • PowerPC core with floating-point unit • 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM • 448 ...
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Interface RCPU 16 Kbytes SRAM QADC QADC TPU3 DPTRAM Figure 1-1 MPC555 / MPC556 Block Diagram 1.2 MPC555 / MPC556 Features Features of each module on the MPC555 / MPC556 are listed below. 1.2.1 RISC MCU Central Processing Unit (RCPU) ...
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On-chip emulation (OnCE 1.2.2 Four-Bank Memory Controller • Works with SRAM, EPROM, flash EEPROM, and other peripherals • Byte write enables • 32-bit address decodes with bit masks • Memory transfer start (MTS): This pin is the transfer start ...
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General-Purpose I/O Support • Address (24) and data (32) pins can be used for general-purpose I/O in single- chip mode • 9 general-purpose I/O pins in MIOS1 unit • Many peripheral pins can be used for general-purpose I/O when ...
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Two CAN 2.0B Controller Modules (TouCANs) Each TouCAN provides these features: • Full implementation of CAN protocol specification, version 2.0 A and B • Each module has 16 receive/transmit message buffers bytes data length • ...
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Figure location allows the user to implement a multiple-chip system. 0x0000 0000 0x003F FFFF 0x0040 0000 0x007F FFFF 0x0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 0x013F FFFF 0x0140 0000 0x017F FFFF 0x0180 0000 ...
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CMF Flash A 256 Kbytes 0x04 0000 CMF Flash B Kbytes 192 0x06 FFFF 0x07 0000 Reserved for Flash (2.6 Mbytes - 16 Kbytes) BFFF 000 & ash ...
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MPC555 MPC556 USER’S MANUAL OVERVIEW Rev. 15 October 2000 MOTOROLA 1-8 ...
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Packaging and Pinout Descriptions Figure 2-1 gives the case configuration and packaging information for the MPC555 / MPC556. Figure 2-2 gives the MPC555 / MPC556 pinout data. overview of the pins on the MPC555 / MPC556. MPC555 / MPC556 ...
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PIN 1 D INDEX 0 TOP VIEW (D1) 19X e 19X (E1 BOTTOM VIEW ...
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Figure 2-2 MPC555 / MPC556 Pinout Data / MPC555 MPC556 USER’S MANUAL SIGNAL DESCRIPTIONS Rev. 15 October 2000 MOTOROLA 2-3 ...
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Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA Functional Group 24 Address lines (16-Mbyte address space) 32-bit data bus External interrupts Bus control General purpose chip select ma- chine (multiplexed with development and debug support) Power-on reset and ...
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Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued) Functional Group Clocks and PLL QSMCM MIOS General-Purpose I/O from MIOS TPU QADC TouCAN Flash EEPROM Ground Analog Ground Low Voltage Supply / MPC555 MPC556 USER’S MANUAL 1 Signals ...
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Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued) Functional Group High voltage Supply Programming Voltage NOTES: 1. “/” implies that the corresponding functions are multiplexed on the pin 2. All inputs are 5 V friendly. All 5 ...
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Table 2-2 Pin Functionality Table Pin Function ADDR[8:31] ADDR[8:31]/ SGPIOA[8:31] SGPIOA[8:31] DATA[0:31] DATA[0:31] SGPIOD[0:31] SGPIOD[0:31] IRQ[0] IRQ[0]/ SGPIOC[0] SGPIOC[0] IRQ[1] IRQ[1]/RSV/ RSV SGPIOC[1] SGPIOC[1] IRQ[2] IRQ[2]/CR/ CR SGPIOC[2]/ MTS SGPIOC[2] MTS IRQ[3] IRQ[3]/KR, RETRY/ KR, RETRY SGPIOC[3] SGPIOC[3] IRQ[4] IRQ[4]/AT[2]/ ...
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Table 2-2 Pin Functionality Table (Continued) Pin Function BDIP BDIP TEA TEA RSTCONF RSTCONF/ 2 TEXP TEXP BI/STS STS CS[0:3] CS[0:3] WE[0:3]/BE[0:3] WE[0:3]/ BE[0:3]/AT[0:3] AT[0:3] 2 PORESET PORESET 2 HRESET ...
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Table 2-2 Pin Functionality Table (Continued) Pin Function TCK TCK/DSCK DSCK TDO TDO/DSDO DSDO TRST TRST 2 XTAL XTAL 2 EXTAL EXTAL XFC XFC CLKOUT CLKOUT 2 EXTCLK EXTCLK ENGCLK ENGCLK/ BUCLK BUCLK PCS0 PCS0/ SS SS/QGPIO[0] QGPIO[0] PCS[1:3] PCS[1:3]/ ...
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Table 2-2 Pin Functionality Table (Continued) Pin Function MPWM[0:3], MPWM[0:3], [16:19] [16:19] VF[0:2] VF[0:2]/ MPIO32B[0:2] MPIO32B[0:2] VFLS[0:1] VFLS[0:1]/ MPIO32B[3:4] MPIO32B[3:4] MPIO32B[5:15] MPIO32B[5:15] A_TPUCH[0:15] TPUCH[0:15] A_T2CLK T2CLK B_TPUCH[0:15] TPUCH[0:15] B_T2CLK T2CLK ETRIG[1:2] ETRIG[1:2] AN0 AN0/ ANW ANW/ PQB0 PQB0 AN1 ANX ...
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Table 2-2 Pin Functionality Table (Continued) Pin Function AN[55:56] AN[55:56]/ PQA[3:4] PQA[3:4] AN[57:59] AN[57:59]/ PQA[5:7] PQA[5:7] AN0 AN0/ANW/ ANW PQB0 PQB0 AN1 ANX AN1/ANX/PQB1 PQB1 AN2 ANY AN2/ANY/PQB2 PQB2 AN3 ANZ AN3/ANZ/PQB3 PQB3 AN[48:51] AN[48:51]/ PQB[4:7] PQB[4:7] AN[52:54] AN[52:54]/ MA[0:2] ...
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Table 2-2 Pin Functionality Table (Continued) Pin Function EPEE EPEE VPP VPP VDDA VDDA VDDF VDDF VDDL VDDL VDDH VDDH VDDI VDDI VDDSYN VDDSYN VRH VRH VRL VRL VSSA VSSA VSSF VSSF VSSSYN VSSSYN 2 KAPWR KAPWR VDDSRAM VDDSRAM VSS ...
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SGPIO – This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.2 DATA[0:31]/SGPIOD[0:31] Pin Name: data_sgpiod[0:31] (32 pins) Data Bus – Provides the general purpose data path between the chip and all other devices. Although the data ...
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Interrupt Request – One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Kill Reservation – In case of a bus cycle initiated by a STWCX instruction issued ...
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Transfer size – Indicates the size of the requested data transfer in the current bus cy- cle. 2.3.1.11 RD/WR Pin Name: rd_wr_b Read/Write – Indicates the direction of the data transfer for a transaction. A logic one indicates a read ...
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Transfer Error Acknowledge – This signal indicates that a bus error occurred in the current transaction. The MCU asserts this signal when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. The assertion ...
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WE[0:3]/BE[0:3]/AT[0:3] Pin Name: we_b_at[0:3](4 pins) Write Enable[0:3]/Byte Enable[0:3] – This output line is asserted when a write ac- cess to an external slave controlled by the GPCM in the memory controller is initiated by the chip. It can be ...
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SGPIO – This function allows the pins to be used as general purpose inputs/outputs. Freeze – Indicates that the RCPU is in debug mode. Program Trace – Indicates an instruction fetch is taking place in order to allow pro- gram ...
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Bus Busy – Indicates that the master is using the bus. This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. Visible Instruction Queue Flush Status – This ...
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Test Data Out – This output is used for serial test instructions and test data for on- board test logic (JTAG). Development Serial Data Output – This output line is the data-out line of the debug port interface. See SECTION ...
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VDDSYN – This is the power supply of the PLL circuitry. 2.3.1.42 VSSSYN Pin Name: vsssyn VSSSYN – This is the power supply of the PLL circuitry. 2.3.1.43 ENGCLK/BUCLK Pin Name: engclk_buclk ENGCLK – This is the engineering clock output. ...
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MOSI/QGPIO[5] Pin Name: mosi_qgpio5 Master-Out Slave-In (MOSI) – This bi-directional signal furnishes serial data output from the QSPI in master mode and serial data input to the QSPI in slave mode. QGPIO[5] – When this pin is not needed ...
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MIOS PADS 2.3.3.1 MDA[11], [13] Pin Name: mda11, mda13 (2 pins) Double Action – Each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. Clock Input – Each of these pins provide ...
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Visible History Buffer Flush Status – These signals are output by the chip to allow program instruction flow tracking. They report the number of instructions flushed from the history buffer in the RCPU. See tails. MIOS GPIO – This function ...
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Port (PQB0) – Input-only port. This is a 5-V input. This path is synchronized in the pad. The input is level-shifted before it is sent internally to the QADC. 2.3.5.3 AN[1]/ANX/PQB[1]_[A:B] Pin Name: a_an1_anx_pqb1 (1 pin for first QADC), b_an1_anx_pqb1 ...
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AN[52:54]/MA[0:2]/PQA[0:2]_[A:B] Pin Name: a_an52_ma0_pqa0 – a_an54_ma2_pqa2 (3 pins for first QADC), b_an52_ma0_pqa0 – b_an54_ma2_pqa2 (3 pins for second QADC). Analog Input (AN[52:54]) – Input-only. The input is passed separate signal to the QADC. Multiplexed Address (MA[0:2]) ...
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TouCAN Transmit Data 0 – This signal is the serial data output. 2.3.6.2 CNRX0_[A:B] Pin Name: a_cnrx0 (1 pin for first CAN), b_cnrx0 (1 pin for second CAN) TouCAN Receive Data – This signal furnishes serial input data. 2.3.7 CMF ...
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VDDI Pin Name: vddi VDDI – 3-V voltage supply input for internal logic. 2.3.8.4 VSSI Pin Name: vssi VSSI – Zero supply input for internal logic. In packaged devices, VSSI is not a sepa- rate input from VSS. 2.3.8.5 ...
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The bus pin drive selectability definition is inverted from the selectability of the pin control in the PDMCR register (for the ...
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Table 2-3 PDMCR Bit Descriptions (Continued) Bit(s) Name The SPRDS bit is used to enable or disable the weak pull-up/pull-down devices in special 3-V only bus pads. 7 SPRDS this bit affects the pins see 0 = Enable pull-up/pull-down devices ...
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Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins Two signals are needed to enable or disable the pull-up/pull-down devices in the 3-V / 5-V multiplexed pads: • The PRDS signal • An encoded 3-V / ...
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Special Pull Resistor Disable Control (SPRDS) For the pins that support debug and opcode-tracking functionality, the pull-up and pull- down resistors are controlled by the SPRDS signal, which is somewhat like the encod- ed 3-V / 5-V select. During ...
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Table 2-4 Pin Reset State (Continued) Pin Function IRQ[5] IRQ[5]/SGPIOC[5]/ SGPIOC[5] 3 MODCK[1] MODCK[1] IRQ[6:7] IRQ[6:7]/ 3 MODCK[2:3] MODCK[2:3] TSIZ[0:1] TSIZ[0:1] RD/WR RD/WR BURST BURST BDIP BDIP TEA TEA RSTCONF 3 RSTCONF/TEXP TEXP OE ...
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Table 2-4 Pin Reset State (Continued) Pin Function SGPIOC[7] SGPIOC[7/ IRQOUT IRQOUT/LWP[0] LWP[0] BG BG/ VF[0]/ VF[0] LWP[1] LWP[1] BR BR/ VF[1]/ VF[1] IWP[2] IWP[2] BB BB/ VF[2]/ VF[2] IWP[3] IWP[3] IWP[0:1] IWP[0:1]/ VFLS[0:1] VFLS[0:1] TMS TMS TDI TDI/ DSDI ...
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Table 2-4 Pin Reset State (Continued) Pin Function PCS0 PCS0/ SS/ SS QGPIO[0] QGPIO[0] PCS[1:3] PCS[1:3]/ QGPIO[1:3] QGPIO[1:3] MISO MISO/ QGPIO[4] QGPIO[4] MOSI MOSI/ QGPIO[5] QGPIO[5] SCK SCK/ QGPIO[6] QGPIO[6] TXD[1:2] TXD[1:2]/ QGPO[1:2] QGPO[1:2] RXD[1:2] RXD[1:2]/QGPI[1:2] QGPI[1:2] ECK ECK MDA[4:13] ...
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Table 2-4 Pin Reset State (Continued) Pin Function AN3 A: AN3/ANZ/PQB3 ANZ PQB3 AN[48:51] A: AN[48:51]/ PQB[4:7] PQB[4:7] AN[52:54] A: AN[52:54]/ MA[0:2] MA[0:2]/PQA[0:2] PQA[0:2] AN[55:56] A: AN[55:56]]/ PQA[3:4] PQA[3:4] AN[57:59] A: AN[57:59]/ PQA[5:7] PQA[5:7] AN0 B: AN0/ANW/PQB0 ANW PQB0 AN1 ...
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Table 2-4 Pin Reset State (Continued) Pin Function EPEE EPEE VPP VPP VDDF VDDF VSSF VSSF VDDL VDDL VDDH VDDH VDDI VDDSI VSSI VSSI 3 KAPWR KAPWR VDDSRAM VDDSRAM VDDSYN VDDSYN VSS VSS VSSSYN VSSSYN NOTES: 1. During reset, the ...
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Drive select – Selects the drive strength of the pad. For example, data pin drivers can be configured to drive a 25-pF load or a 50-pF load. • Synchronizer clock – Some pins have synchronizer logic to handle metastable ...
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Drive Sel Sprds Data Out Logic OE 2.5.2.2 Type B Interface (Clock Pad) The pad has a capability to select the buffer for the appropriate load ( pF). The OE input drives the totem pole output or three-states ...
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The SPRDS signal may disable the pull-up or pull-down resistor. 2.5.3.1 Type C Interface The type C interface has a 3-V input with a pull-up resistor. Data In Sprds 2.5.3.2 Type CH ...
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Type CNH Interface The CNH pad type has a 3-V input with hysteresis but no pull-up or pull-down device. Data In 2.5.3.4 Type D Interface This type of pad has a 3-V input and an internal pull-down resistor. Data ...
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Type E Interface In this pad type the data interface to the internal logic has separate paths for input and output. This pad also has a open drain enable input. For totem pole driven outputs, the signal is connected ...
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Drive Sel Sprds Data Out Logic OE Data In IE Figure 2-10 3-V Type EOH Interface 2.5.4.3 Type F Interface In this pad type the data interface to the internal logic has the same path for both input and output. ...
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Drive Sel Sprds Data IO Logic OE IE 2.5.4.4 Type G Interface In this pad type the data interface to the internal logic has the same path for both input and output. This pad type also has the SPRDS signal ...
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Sprds Drive Sel Data Out Logic OE Data In IE 2.5.5 Five-Volt Input/Output Pad This pad type is for 5-V bi-directional pins. There is provision to pull the pin and logic to control when the pull-up ...
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Sel PRDS Drive Sel 5 V Data Out Logic 3 V Data Out OE SLRC Synch. Data In Synch. Clk 2.5.5.2 Type I Interface This pad has logic for a 3-V input/output function as well as a ...
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Sel PRDS Data Out Logic OE Drive Sel SLRC Data In IE 2.5.5.3 Type IH Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” ...
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Sel PRDS Data Out Logic OE Drive Sel SLRC Data In IE hyst_sel 2.5.5.4 Type J Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V ...
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Sel PRDS Data Logic OE Drive Sel SLRC IE 2.5.5.5 Type JD Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” interface signal indicates ...
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Sel PRDS Data Logic OE Drive Sel SLRC IE 2.5.6 Type K Interface (EPEE Pad) This pad has a pull-down device that is enabled at all times. The module checks to see that a transition to a ...
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Data Synch. Clk Figure 2-18 EPEE Pad (Type K) 2.5.7 Analog Pads The 5-V analog pads interface to the QADC modules internally. They have separate analog and digital paths in the pad in order to implement the functionality that is ...
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PRDS Analog In Dig. Out Data Direction Dig. In Input Enable Sync. Clk 2.5.7.2 Type M Interface (QADC Port B) This pad is used for interfacing to port B of the QADC. This is an input-only pad. The receiver has ...
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Type N Interface (ETRIG) This is the pad for the ETRIG function of the QADC. The input signal is level-shifted before being sent to the QADC module. The pad also serves as an output pad in test mode. Input ...
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SLRC OD Enable PRDS Data Out Logic OE Normal Data In Synch. Data In Synch. Clk 2.5.8.2 Type P Interface (TPU and MIOS Pads) This is a 5-V, bi-directional pad that has a fast mode provision like the QSMCM pads. ...
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SLRC PRDS Data Out Logic OE Synch. Data In Synch. Clk 2.5.9 5V Input, 5V Output Pads These pads are 5-V only pads. 2.5.9.1 5V Output (Type Q) This pad is a 5-V output-only pad with slow and fast drive ...
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PRDS OD Enable Data Out Logic OE SLRC 2.5.9.2 Type R Interface This is a 5-V input-only pad with a synchronous and asynchronous receiver. Both syn- chronous and asynchronous data are driven in from the internal module that interfaces to ...
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Output for Clock Pad This interface is used for a 5-V clock pad output. The drive select signal selects the buffer for a 45- or 90-pF load. Drive Sel Data Out Logic OE 2.6 Pad Groups A pad ...
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Pin Names and Abbreviations The following table lists the recommended abbreviations for all the pins on the MPC555 / MPC556. The abbreviations can be used in applications for which the actual name is too long. For example, they can ...
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Table 2-6 Pin Names and Abbreviations (Continued) Pin List DATA[0:31]/SGPIOD[0:31] IRQ[0]/SGPIOC[0] IRQ[1]/RSV/SGPIOC[1] IRQ[2]/CR/SGPIOC[2]/MTS IRQ[3]/KR, RETRY/SGPIOC[3] IRQ[4]/AT[2]/SGPIOC[4] IRQ[5]/SGPIOC[5]/MODCK[1] IRQ[6:7]/MODCK[2:3] TSIZ[0:1] / MPC555 MPC556 USER’S MANUAL Pin Name data_sgpiod[0] data_sgp[0] data_sgpiod[1] data_sgp[1] data_sgpiod[2] data_sgp[2] data_sgpiod[3] data_sgp[3] data_sgpiod[4] data_sgp[4] data_sgpiod[5] data_sgp[5] data_sgpiod[6] data_sgp[6] ...
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Table 2-6 Pin Names and Abbreviations (Continued) Pin List RD/ WR BURST BDIP TS TA TEA RSTCONF/TEXP OE BI/STS CS[0:3] WE[0:3]/BE[0:3]/AT[0:3] PORESET HRESET SRESET SGPIOC[6]/FRZ/PTR/ SGPIOC[7]/IRQOUT/LWP[0] BG/VF[0]/LWP[1] BR/VF[1]/IWP[2] BB/VF[2]/IWP[3] IWP[0:1]/VFLS[0:1] TMS TDI/DSDI TCK/DSCK TDO/DSDO TRST XTAL EXTAL XFC CLKOUT EXTCLK ...
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Table 2-6 Pin Names and Abbreviations (Continued) Pin List PCS0/SS/QGPIO[0] PCS[1:3]/QGPIO[1:3] MISO/QGPIO[4] MOSI/QGPIO[5] SCK/QGPIO[6] TXD[1:2]/QGPO[1:2] RXD[1:2]/QGPI[1:2] ECK MDA[11:15] MDA[27:31] MPWM[0:3], [16:19] VF[0:2]/MPIO32B[0:2] VFLS[0:1]/MPIO32B[3:4] / MPC555 MPC556 USER’S MANUAL Pin Name QSMCM pcs0_ss_b_qgpio0 pcs0_qgp pcs1_qgpio1 pcs1_qgp pcs2_qgpio2 pcs2_qgp pcs3_qgpio3 pcs3_qgp miso_qgpio4 ...
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Table 2-6 Pin Names and Abbreviations (Continued) Pin List MPIO32B[5:15] A: TPUCH[0:15] A: T2CLK / MPC555 MPC556 USER’S MANUAL Pin Name mpio32b5 mpio5 mpio32b6 mpio6 mpio32b7 mpio7 mpio32b8 mpio8 mpio32b9 mpio9 mpio32b10 mpio10 mpio32b11 mpio11 mpio32b12 mpio12 mpio32b13 mpio13 mpio32b14 ...
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Table 2-6 Pin Names and Abbreviations (Continued) Pin List B: TPUCH[0:15] B: T2CLK ETRIG[1:2] A: AN0/ANW/PQB0 A: AN1/ANX/PQB1 A: AN2/ANY/PQB2 A: AN3/ANZ/PQB3 A: AN[48:51]/PQB[4:7] A: AN[52:54]/MA[0:2]/PQA[0:2] A: AN[55:56]]/PQA[3:4] A: AN[57:59]/PQA[5:7] B: AN0/ANW/PQB0 B: AN1/ANX/PQB1 B: AN2/ANY/PQB2 B: AN3/ANZ/PQB3 / MPC555 ...
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Table 2-6 Pin Names and Abbreviations (Continued) Pin List B: AN[48:51]/PQB[4:7] B: AN[52:54]/MA[0:2]/PQA[0:2] B: AN[55:56]/PQA[3:4] B: AN[57:59]/PQA[5:7] VRH VRL VDDA VSSA A: CNTX0 B: CNTX0 A: CNRX0 B: CNRX0 EPEE VPP VDDF VSSF VDDL VDDH VDDI KAPWR VDDSRAM VSS / ...
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CENTRAL PROCESSING UNIT The PowerPC-based RISC processor (RCPU) used in the MPC500 family of micro- controllers integrates five independent execution units: an integer unit (IU), a load/ store unit (LSU), and a branch processing unit (BPU), floating-point unit (FPU) and ...
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RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU. RCPU L-DATA L-ADDR INSTRUCTION SEQUENCER INSTRUCTION PRE-FETCH QUEUE I-DATA BRANCH PROCESSOR UNIT I-ADDR NEXT ADDRESS GENERATION Figure 3-1 RCPU Block Diagram / MPC555 MPC556 USER’S MANUAL LOAD/STORE ...
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Instruction Sequencer The instruction sequencer provides centralized control over data flow between execu- tion units and register files. The sequencer implements the basic instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains ...
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INSTRUCTION ADDRESS GENERATOR EXECUTION UNITS AND REGISTERS FILES Figure 3-2 Sequencer Data Path 3.4 Independent Execution Units The PowerPC architecture supports independent floating-point, integer, load/store, and branch processing execution units, making it possible to implement advanced fea- tures such as ...
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Table 3-1 RCPU Execution Units Unit Branch processing Includes the implementation of all branch instructions unit (BPU) Includes implementation of all load and store instructions, whether defined as part Load/store unit (LSU) of the integer processor or the floating-point processor ...
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The IU also includes the integer exception register (XER) and the general-purpose register file. IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU– BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require multiple clock cycles ...
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Levels of the PowerPC Architecture The PowerPC architecture consists of three layers. Adherence to the PowerPC archi- tecture can be measured in terms of which of the following levels of the architecture are implemented: • PowerPC user instruction set ...
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USER MODEL UISA FPR0 FPR1 FPR31 0 GPR0 Condition GPR1 Register CR 0 GPR31 31 0 Floating-Point Status and Control Register FPSCR 0 User-Level SPRs Integer Exception Register (XER) Link Register (LR) Count Register (CTR) 0 USER MODEL VEA Time ...
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Table 3-2 Supervisor-Level SPRs SPR Number (Decimal 272 273 274 275 284 285 287 528 536 560 / MPC555 MPC556 USER’S MANUAL Special-Purpose Register DAE/Source Instruction Service Register (DSISR) See 3.9.2 DAE/Source ...
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Table 3-2 Supervisor-Level SPRs (Continued) SPR Number (Decimal) 568 784 785 786 787 792 793 794 795 816 817 818 819 824 825 826 827 1022 NOTES: 1. Implementation-specific SPR. Table 3-3 lists the MPC555 / MPC556 SPRs used for ...
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Table 3-3 Development Support SPRs SPR Number (Decimal) 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 630 NOTES: 1. All development-support SPRs are implementation-specific. Where not otherwise noted, reserved fields in registers ...
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General-Purpose Registers (GPRs) Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below. These registers are accessed as source and destination registers through operands in the instruction syntax. GPRs — General-Purpose Registers MSB ...
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FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are sticky, except for the floating-point enabled exception summary (FEX) and float- ing-point invalid operation exception summary (VX). Once set, sticky bits remain set until they are cleared by an ...
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Table 3-5 FPSCR Bit Descriptions Bit(s) Name Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if that instruction causes any of the floating-point exception bits in the FPSCR to change from The mcrfs instruction ...
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Table 3-5 FPSCR Bit Descriptions (Continued) Bit(s) Name Floating-point invalid operation exception for software request. This bit can be altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow soft- 21 VXSOFT ...
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CR — Condition Register MSB CR0 CR1 The CR ...
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Table 3-8 Bit Descriptions for CR1 Field of CR CR1 Bit Floating-point exception (FX) — This is a copy of the final state of FPSCR[FX] at the completion of the in- 0 struction. Floating-point enabled exception (FEX) — This is ...
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The bit definitions for XER, shown in struction considered as a whole, not on intermediate results. For example, the result of the Subtract from Carrying (subfcx) instruction is specified as the sum of three val- ues. This instruction sets bits ...
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Count Register (CTR) The count register (CTR 32-bit register for holding a loop count that can be dec- remented during execution of branch instructions that contain an appropriately coded BO field. If the value in CTR is ...
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PowerPC OEA Register Set The PowerPC operating environment architecture (OEA) includes a number of SPRs and other registers that are accessible only by supervisor-level instructions. Some SPRs are RCPU-specific; some RCPU SPRs may not be implemented in other Pow- ...
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Table 3-12 Machine State Register Bit Descriptions Bit(s) Name 0:12 — Reserved Power management enable 13 POW 0 = Power management disabled (normal operation mode Power management enabled (reduced power mode) 14 — Reserved Exception little-endian mode. When ...
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Table 3-12 Machine State Register Bit Descriptions (Continued) Bit(s) Name 28 — Reserved Decompression On/Off DC RCPU Normal Operation 1 MPEN 1 = RCPU is running in Compressed mode Recoverable exception (for machine check and non-maskable breakpoint ...
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Time Base Facility (TB) — OEA As described in 3.8 PowerPC VEA Register Set — Time provides a 64-bit incrementing counter. The VEA defines user-level, read-only access to the TB. Writing to the TB is reserved for supervisor-level applications ...
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MPC555 / MPC556, refer to MPC555 / MPC556 Internal Clock ister (SCCR). The DEC does not run after power-up and must be enabled by setting the TBE bit in the TBSCR register, see register. A decrementer exception ...
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SRR1 — Machine Status Save/Restore Register 1 MSB ...
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Table 3-16 Processor Version Register Bit Descriptions Bit(s) Name A 16-bit number that identifies the version of the processor and of the PowerPC architec- 0:15 VERSION ture. MPC555 / MPC556 value is 0x0002. A 16-bit number that distinguishes between various ...
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FPECR — Floating-Point Exception Cause Register MSB SIE RESET RESET listing of FPECR bit descriptions is shown in Table ...
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Instruction Set All PowerPC instructions are encoded as single words (32 bits). Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly sim- ...
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Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory con- tents must be loaded into a register, modified, and then written back to the ...
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Table 3-19 Instruction Set Summary (Continued) Mnemonic crorc crxor divw (divw. divwo divwo.) divwu divwu. divwuo divwuo. eieio eqv (eqv.) extsb (extsb.) extsh (extsh.) fabs (fabs.) fadd (fadd.) fadds (fadds.) fcmpo fcmpu fctiw (fctiw.) fctiwz (fctiwz.) fdiv (fdiv.) fdivs (fdivs.) ...
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Table 3-19 Instruction Set Summary (Continued) Mnemonic lfdux lfdx lfs lfsu lfsux lfsx lha lhau lhaux lhax lhbrx lhz lhzu lhzux lhzx lmw lswi lswx lwarx lwbrx lwz lwzu lwzux lwzx mcrf mcrfs mcrxr mfcr mffs (mffs.) mfmsr mfspr mftb ...
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Table 3-19 Instruction Set Summary (Continued) Mnemonic mulli mullw (mullw. mullwo mullwo.) nand (nand.) neg (neg. nego nego.) nor (nor.) or (or.) orc (orc.) ori oris rfi rlwimi (rlwimi.) rlwinm (rlwinm.) rlwnm (rlwnm.) sc slw (slw.) sraw (sraw.) srawi (srawi.) ...
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Table 3-19 Instruction Set Summary (Continued) Mnemonic stwbrx stwcx. stwu stwux stwx subf (subf. subfo subfo.) subfc (subfc. subfco subfco.) subfe (subfe. subfeo subfeo.) subfic subfme (subfme. subfmeo subfmeo.) subfze (subfze. subfzeo subfzeo.) sync tw twi xor (xor.) xori xoris ...
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For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the storage operand is considered to wrap around from the maximum effective address to effective address 0. Effective address ...
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SRR0 and SRR1 (and, in some cases, the DAR and DSISR) may not be recoverable; the processor may ...
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Table 3-21 Exception Vector Offset Table Vector Offset (Hexadecimal) 00000 00100 00200 00300 00400 00500 00600 00700 00800 00900 00A00 00B00 00C00 00D00 00E00 01000 01100 01200 01300 01400 01500–01BFF 01C00 01D00 01E00 01F00 3.12 Instruction Timing The MPC555 / ...
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In the execute stage, each execution unit that has an executable instruction ex- ecutes the instruction. (For some instructions, this occurs over multiple cycles the writeback stage, the execution unit writes the result to the destination reg- ...
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Table 3-22 Instruction Latency and Blockage Instruction Type Floating-point multiply-add Floating-point add or subtract Floating-point multiply Floating-point divide Integer multiply Integer divide Integer load/store NOTES: Section 7 Instruction Timing, 1. Refer to Manual (RCPURM/AD) 3.13 PowerPC User Instruction Set Architecture ...
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Invalid and preferred instruction forms treatment by the MPC555 / MPC556 is described under the specific processor compli- ance sections. 3.13.4 Exceptions Invocation of the system software for any instruction-caused exception in the MPC555 / MPC556 ...
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Fixed-point rotate and shift instructions • Move to/from system register instructions All instructions are defined for the fixed-point processor in the UISA in the hardware. For performance of the various instructions, refer to — Move To/From System Register Instructions. ...
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Fixed-Point Load With Update and Store With Update Instructions For load with update and store with update instructions, where the EA is writ- ten into R0. For load with update instructions, where RA = RT, RA ...
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The following check is done on the stored operand in order to determine whether denormalized single-precision operand and invoke the floating-point assist interrupt handler handler: Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete ...
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Enforce In-Order Execution of I/O (eieio) Instruction When executing an eieio instruction, the load/store unit will wait until all previous ac- cesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction. 3.14.5 Timebase A description ...
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DBAT3U, DBAT3L • Added Registers — For a list of added special purpose registers, refer to 3-2, and Table 3-3. 3.15.3 Storage Control Instructions Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlb- sync are not implemented ...
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Machine Check Interrupt A machine check interrupt indication is received from the U-bus as a possible re- sponse either to the address or data phase usually caused by one of the following conditions: • The accessed address ...
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Register Name Data/Storage Interrupt Status Register (DSISR) Data Address Register (DAR) 3.15.4.4 Instruction Storage Interrupt An instruction storage interrupt is never generated by the hardware. The software may branch to this location as a result of an implementation-specific instruction storage ...
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Floating-Point Unavailable Interrupt The floating-point unavailable interrupt is generated by the MPC555 / MPC556 core as defined in the OEA. 3.15.4.10 Trace Interrupt A trace interrupt occurs if MSR pleted or MSR = 1 and a branch is completed. ...
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Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) NOTES the current implementation bit 30 of the SRR1 is never cleared other then by loading zero value from MSR RI. 3.15.4.12 Implementation-Dependent Software ...
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Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Execution resumes at offset 0x01000 from the base address indicated by MSR 3.15.4.13 Implementation-Specific Instruction Storage Protection Error Interrupt The implementation-specific instruction storage protection error interrupt ...
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Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Execution resumes at offset 0x01300 from the base address indicated by MSR 3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt The implementation-specific data storage protection error interrupt ...
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Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Data/Storage Interrupt Status Register (DSISR) Data Address Register (DAR) Execution resumes at offset 0x01400 from the base address indicated by MSR 3.15.4.15 Implementation-Specific Debug Interrupts Implementation-specific ...
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Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) For L-bus breakpoint instances, these registers are set to: Register Name BAR DAR and DSISR Execution resumes at offset from the base address indicated by MSR ...
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Multiple/string instructions • Unaligned load/store instructions In the last case, the store instruction can be partially completed if one of the accesses (except the first one) causes the data storage protection error. The implementation- specific data storage protection interrupt ...
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MPC555 MPC556 USER’S MANUAL CENTRAL PROCESSING UNIT Rev. 15 October 2000 MOTOROLA 3-54 ...
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The burst buffer module consists of the burst buffer controller (BBC) and the instruc- tion memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline ...
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RCPU InstructionAddress Bus Figure 4-1 Burst Buffer Block Diagram 4.2 Burst Buffer Features The BBC offers the following features: • Supports pipelined access to internal memory and burstable access to the exter- nal memory. • Supports the de-coupled interface with ...
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Minimal performance penalty due to change of program flow execution • Two operation modes are available: “Decompression ON” and “Decompression OFF”. Switch between compressed and non-compressed user application soft- ware parts is possible. The IMPU has the following features: ...
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Slight changes in the core and existing RISC development tools — compilers, simulators, manually coded libraries. • Compressed address space four Megabytes (4 Mbytes). • Branch displacement from its target: — Conditional branch displacement is up ...
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Original Code Figure 4-2 Example of Compressed Code Each instruction is divided to four bytes, marked X1, X2, X3 and X4. For each such byte a separate (Huffman ...
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Memory Organization In order to enhance performance, the logic is built to decode two halves of an instruc- tion in parallel. The memory is arranged to support this as two streams of compressed symbols: the left stream for the ...
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The compiler will set the left and right stream boundary at either bit 12 or bit 19. This will be determined by the most efficient placement of compressed instruction code. The boundary will be placed between bits 11 and 12 ...
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Compressed Code Address Format The format of the compressed code in memory requires special addressing. The Decompressor module is responsible for generating compressed code addresses. The compressed instruction stream may start on any of the 32 bits. Thus, five ...
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Base Address x x+4 0 Left/Right = X (don’t care) ( Left and Right are at the base address), Same_Line = 0 Base Address x x+4 0 Left/Right = 1 (Right side is first at the base address), Same_Line = ...
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This will yield a conditional branch displacement limit of two Kbytes. When a change of flow occurs, the sequencer of the PPC core will issue the new ad- dress in compression mapped format. The address extractor ...
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An instruction in memory which will serve as the target of a branch will have a label attached. The label provides the needed pointer to the other half of the branch target instruction. The label token will be skipped in ...
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The resulting uncompressed elf code (with compression hooks) will load and run like any other elf code. The software compression tool compresses the elf code (x.elf) and produces a com- pressed elf code (x.elf.sqz). The system sees the ...
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BYPS_node Figure 4-12 Bounded Huffman Code Tree In Figure 4-12, instruction “a” would require two bits. The bypass node would require four bits. ...
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Compressed Instructions Memory COF Word-Aligned Physical Address Compressed Instruction Code Figure 4-13 Code Decompression Process 4.3.10 Compression Environment Initialization At power on reset (POR) or with a hard reset, the default settings will be activated unless the configuration word inputs ...
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Normal Operation During normal operation, the burst buffer module transfers fetch accesses from the CPU to the U-bus. When a new access is issued by the CPU transferred in parallel to both the IMPU and the BBC. ...
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The BE bit defined in 4.6.4 BBC Module Configuration Register (BBCMCR) mines whether the BBC operates burst cycles or not. Burst requests are enabled only when the BE bit is set. The negated state of the BE bit is useful ...
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Exception Table Relocation Operation When an exception is requested, the CPU initiates a fetch cycle that branches to the exception routine associated with the exception that caused the fetch. The exception addresses are fixed within the RCPU architecture and ...
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Table 4-1 Exception Addresses Mapping by BBC Name of Exception Reserved System Reset Machine Check Data Storage Instruction Storage External Interrupt Alignment Program Floating Point unavailable Decrementer Reserved Reserved System Call Trace Floating Point Assist Implementation Dependant Software Emulation Implementation ...
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Exception Pointer by RCPU 0 100 200 300 400 500 600 700 1F00 Figure 4-14 Exception Table Entries Mapping / MPC555 MPC556 USER’S MANUAL Internal Memory Structure F8 Main code can start here BURST BUFFER Rev. 15 October 2000 branch ...
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Burst Buffer Programming Model The BBC and IMPU module configuration registers are MPC555 / MPC556 special- purpose registers (SPRs). They are programmed with the MPC555 / MPC556 mtspr/ mfspr instructions. All the registers can be accessed in supervisor mode ...
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Region Base Address Registers MI_RBA[0:3] — Region Base Address Register MSB RESET RESET: Table 4-5 MI_RBA[0:3] Bit Descriptions Bit(s) Name 0:19 RA Region address. This field defines the ...
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Table 4-6 MI_RA[0:3] Registers Bits Description Bit(s) Name Region size. The region size is a power of two, determined as follows: 0000_0000_0000_0000_0000 — 4 Kbytes 0000_0000_0000_0000_0001 — 8 Kbytes 0000_0000_0000_0000_0011 — 16 Kbytes 0000_0000_0000_0000_0111 — 32 Kbytes 0000_0000_0000_0000_1111 — 64 ...
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Global Region Attribute Register Description (MI_GRA) MI_GRA — Global Region Attribute Register MSB ENR0 ENR1 ENR2 ENR3 RESET RESERVED RESET ...
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BBC Module Configuration Register (BBCMCR) BBCMCR — BBC Module Configuration Register MSB RESET RESERVED BE ETRE OERC RE- SET ...