MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 722

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.4.1.1 Debug Mode Enable vs. Debug Mode Disable
21.4.1.2 Entering Debug Mode
MPC555
USER’S MANUAL
For protection purposes two possible working modes are defined: debug mode enable
and debug mode disable. These working modes are selected only during reset.
Debug mode is enabled by asserting the DSCK pin during reset. The state of this pin
is sampled three clocks before the negation of SRESET.
If the DSCK pin is sampled negated, debug mode is disabled until a subsequent reset
when the DSCK pin is sampled in the asserted state. When debug mode is disabled
the internal watchpoint/breakpoint hardware will still be operational and may be used
by a software monitor program for debugging purposes.
When working in debug mode disable, all development support registers (see list in
Table
a monitor debugger software. However, the processor never enters debug mode and,
therefore, the exception cause register (ECR) and the debug enable register (DER)
are used only for asserting and negating the freeze signal. For more information on the
software monitor debugger support refer to
port.
When working in debug mode enable, all development support registers are accessi-
ble only when the CPU is in debug mode. Therefore, even supervisor code that may
be still under debug cannot prevent the CPU from entering debug mode. The develop-
ment system has full control of all development support features of the CPU through
the development port. Refer to
Entering debug mode can be a result of a number of events. All events have a pro-
grammable enable bit so the user can selectively decide which events result in debug
mode entry and which in regular interrupt handling.
Entering debug mode is also possible immediately out of reset, thus allowing the user
to debug even a ROM-less system. Using this feature is possible by special program-
ming of the development port during reset. If the DSCK pin continues to be asserted
following SRESET negation (after enabling debug mode) the processor will take a
breakpoint exception and go directly to debug mode instead of fetching the reset vec-
tor. To avoid entering debug mode following reset, the DSCK pin must be negated no
later than seven clock cycles after SRESET negates. In this case, the processor will
jump to the reset vector and begin normal execution. When entering debug mode im-
mediately after reset, bit 31 (development port interrupt) of the exception cause regis-
ter (ECR) is set.
/
MPC556
21-14) are accessible to the supervisor code (MSRPR = 0) and can be used by
Since SRESET negation is done by an external pull up resistor any
reference here to SRESET negation time refers to the time the
MPC555 / MPC556 releases SRESET. If the actual negation is slow
due to large resistor, set up time for the debug port signals should be
set accordingly.
DEVELOPMENT SUPPORT
Rev. 15 October 2000
Table 21-16
NOTE
21.6 Software Monitor Debugger Sup-
MOTOROLA
21-26