MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 127

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.4.1 Branch Processing Unit (BPU)
3.4.2 Integer Unit (IU)
MPC555
USER’S MANUAL
The following sections describe the execution units in greater detail.
The BPU, located within the instruction sequencer, performs condition register look-
ahead operations on conditional branches. The BPU looks through the instruction
queue for a conditional branch instruction and attempts to resolve it early, achieving
the effect of a zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when an unresolved conditional branch instruction is encountered,
the processor pre-fetches instructions from the predicted target stream until the con-
ditional branch is resolved.
The BPU contains an calculation feature to compute branch target addresses and
three special-purpose, user-accessible registers: the link register (LR), the count reg-
ister (CTR), and the condition register (CR). The BPU calculates the return pointer for
subroutine calls and saves it into the LR. The LR also contains the branch target ad-
dress for the branch conditional to link register (bclrx) instruction. The CTR contains
the branch target address for the branch conditional to count register (bcctrx) instruc-
tion. The contents of the LR and CTR can be copied to or from any GPR. Because the
BPU uses dedicated registers rather than general-purpose or floating-point registers,
execution of branch instructions is independent from execution of integer instructions.
The IU executes all integer processor instructions, except the integer storage access
instructions, which are implemented by the load/store unit. The IU contains the follow-
ing subunits:
Load/store unit (LSU)
Branch processing
Floating-point unit
• The IMUL–IDIV unit includes the implementation of the integer multiply and divide
• The ALU–BFU unit includes the implementation of all integer logic, add and sub-
Integer unit (IU)
/
instructions.
tract, and bit field instructions.
MPC556
unit (BPU)
(FPU)
Unit
Includes the implementation of all branch instructions
Includes implementation of all load and store instructions, whether defined as part
of the integer processor or the floating-point processor
Includes implementation of all integer instructions except load/store instructions.
This module includes the GPRs (including GPR history and scoreboard) and the
following subunits:
The IMUL-IDIV includes the implementation of the integer multiply and divide in-
structions.
The ALU-BFU includes implementation of all integer logic, add and subtract in-
structions, and bit field instructions.
Includes the FPRs (including FPR history and scoreboard) and the implementa-
tion of all floating-point instructions except load and store floating-point instruc-
tions
Table 3-1 RCPU Execution Units
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
Description
MOTOROLA
3-5