MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 249

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.1.4 Loss of Lock
7.1.5 On-Chip Clock Switch
7.1.6 Software Watchdog Reset
7.1.7 Checkstop Reset
7.1.8 Debug Port Hard Reset
7.1.9 Debug Port Soft Reset
7.1.10 JTAG Reset
7.2 Reset Actions Summary
MPC555
USER’S MANUAL
chronous external devices use the MPC555 / MPC556 input clock. Erroneous opera-
tion could also occur if devices with a PLL use the MPC555 / MPC556 CLKOUT signal.
This source of reset can be optionally asserted if the LOLRE bit in the PLL, low-power,
and reset control register (PLPRCR) is set. The enabled PLL loss of lock event gener-
ates an internal hard reset sequence. Refer to
CONTROL
If the system clocked is switched to the backup clock or switched from backup clock
to another clock source an internal hard reset sequence is generated. Refer to
TION 8 CLOCKS AND POWER
When the MPC555 / MPC556 software watchdog counts to zero, a software watchdog
reset is asserted. The enabled software watchdog event generates an internal hard re-
set sequence.
When the RCPU enters a checkstop state, and the checkstop reset is enabled (the
CSR bit in the PLPRCR is set), a checkstop reset is asserted. The enabled checkstop
event generates an internal hard reset sequence. Refer to the
ual (RCPURM/AD)
When the development port receives a hard reset request from the development tool,
an internal hard reset sequence is generated, see
ER
fer to
When the development port receives a soft reset request from the development tool,
an internal soft reset sequence is generated, see
CONTROL. In this case the development tool must reconfigure the debug port. Refer
to
When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset se-
quence is generated, see
SECTION 22 IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
Table 7-1
If the PLL detects a loss of lock, erroneous external bus operation will occur if syn-
SECTION 21 DEVELOPMENT SUPPORT
CONTROL. In this case the development tool must reconfigure the debug port. Re-
/
SECTION 21 DEVELOPMENT SUPPORT
MPC556
summarizes the action taken for each reset.
for more information on loss of lock.
for more information.
SECTION 8 CLOCKS AND POWER
Rev. 15 October 2000
CONTROL.
RESET
for more information.
SECTION 8 CLOCKS AND POWER
SECTION 8 CLOCKS AND POWER
for more information.
SECTION 8 CLOCKS AND POW-
RCPU Reference Man-
for more information.
CONTROL. Refer to
MOTOROLA
SEC-
7-3