MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 301

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Burst data in progress
Special transfer start
Cancel reservation
Kill reservation
Signal Name
Transfer start
/
RETRY
MPC556
BDIP
STS
CR
KR
TS
Table 9-1 MPC555 / MPC556 SIU Signals (Continued)
Pins
1
1
1
1
1
1
EXTERNAL BUS INTERFACE
Active
Low
Low
Low
Low
Low
Low
Rev. 15 October 2000
Reservation Protocol
Transfer Start
I/O
O
O
O
O
I
I
I
I
I
In the case of regular transaction, this signal is driven
by the slave device to indicate that the MPC555 /
MPC556 must relinquish the ownership of the bus and
retry the cycle.
When an external master owns the bus and the inter-
nal MPC555 / MPC556 bus initiates access to the ex-
ternal bus at the same time, this signal is used to
cause the external master to relinquish the bus for one
clock to solve the contention.
Driven by the MPC555 / MPC556 when it owns the
external bus. It is part of the burst protocol. When
BDIP is asserted, the second beat in front of the cur-
rent one is requested by the master. This signal is ne-
gated prior to the end of a burst to terminate the burst
data phase early.
Driven by an external master when it owns the exter-
nal bus. When BDIP is asserted, the second beat in
front of the current one is requested by the master.
This signal is negated prior to the end of a burst to ter-
minate the burst data phase early. The MPC555 /
MPC556 does not support burst accesses to internal
slaves.
Driven by the MPC555 / MPC556 when it owns the
external bus. Indicates the start of a transaction on the
external bus.
Driven by an external master when it owns the exter-
nal bus. It indicates the start of a transaction on the
external bus or (in show cycle mode) signals the be-
ginning of an internal transaction.
Driven by the MPC555 / MPC556 when it owns the
external bus. Indicates the start of a transaction on the
external bus or signals the beginning of an internal
transaction in show cycle mode.
Each PowerPC CPU has its own CR signal. Assertion
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
In case of a bus cycle initiated by a STWCX instruc-
tion issued by the RCPU to a non-local bus on which
the
nal is used by the non-local bus interface to backoff
the cycle. Refer to
tails.
storage reservation
9.5.9 Storage Reservation
Description
has been lost, this sig-
MOTOROLA
for de-
9-5