MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 503

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.8 Mode Fault
14.8 Serial Communication Interface
MPC555
USER’S MANUAL
Wraparound mode is properly exited in two ways: a) The CPU may disable wrap-
around mode by clearing WREN. The next time end of the queue is reached, the QSPI
sets SPIF, clears SPE, and stops; and, b) The CPU sets HALT. This second method
halts the QSPI after the current transfer is completed, allowing the CPU to negate
SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method
is not recommended, as it causes the QSPI to abort a serial transfer in process.
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and
the slave select (PCS[0]/SS) input pin is pulled low by an external driver. This is pos-
sible only if the PCS[0]/SS pin is configured as input by QDDR. This low input to SS is
not a normal operating condition. It indicates that a multimaster system conflict may
exist, that another MCU is requesting to become the SPI network master, or simply
that the hardware is incorrectly affecting PCS[0]/SS. SPE in SPCR1 is cleared, dis-
abling the QSPI. The QSPI pins revert to control by QPDR. If MODF is set and HMIE
in SPCR3 is asserted, the QSPI generates an interrupt to the CPU.
The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing
SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be
re-enabled by asserting SPE.
The PCS[0]/SS pin may be configured as a general-purpose output instead of input to
the QSPI. This inhibits the mode fault checking function. In this case, MODF is not
used by the QSPI.
The dual, independent, serial communication interface (DSCI) communicates with ex-
ternal devices through an asynchronous serial bus. The two SCI modules are function-
ally equivalent, except that the SCI1 also provides 16-deep queue capabilities for the
transmit and receive operations. The SCIs are fully compatible with other Motorola SCI
systems. The DSCI has all of the capabilities of previous SCI systems as well as sev-
eral significant new features.
Figure 14-12
gram of the SCI receiver.
/
MPC556
is a block diagram of the SCI transmitter.
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
Figure 14-13
is a block dia-
MOTOROLA
14-41