MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 339

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.5.10 Bus Exception Control Cycles
9.5.10.1 Retrying a Bus Cycle
MPC555
USER’S MANUAL
The MPC555 / MPC556 bus architecture requires assertion of TA from an external de-
vice to signal that the bus cycle is complete. TA is not asserted in the following cases:
External circuitry can provide TEA when no device responds by asserting TA within an
appropriate period of time after the MPC555 / MPC556 initiates the bus cycle (it can
be the internal bus monitor). This allows the cycle to terminate and the processor to
enter exception-processing for the error condition (each one of the internal masters
causes an internal interrupt under this situation). To properly control termination of a
bus cycle for a bus error, TEA must be asserted at the same time or before TA is as-
serted. TEA should be negated before the second rising edge after it was sampled as
asserted to avoid the detection of an error for the next initiated bus cycle. TEA is an
open drain pin that allows the “wired-or” of any different sources of error generation.
When an external device asserts the RETRY signal during a bus cycle, the MPC555 /
MPC556 enters a sequence in which it terminates the current transaction, relinquishes
the ownership of the bus, and retries the cycle using the same address, address at-
tributes, and data (in the case of a write cycle).
Figure 9-31
is detected as a termination of a transfer. As seen in this figure, in the case when the
internal arbiter is enabled, the MPC555 / MPC556 negates BB and asserts BG in the
clock cycle following the retry detection. This allows any external master to gain bus
ownership. In the next clock cycle, a normal arbitration procedure occurs again. As
shown in the figure, the external master did not use the bus, so the MPC555 / MPC556
initiates a new transfer with the same address and attributes as before.
In
working with an external arbiter. In this case, in the clock cycle after the RETRY signal
is detected asserted, BR is negated together with BB. One clock cycle later, the normal
arbitration procedure occurs again.
Figure
• The external device does not respond
• Various other application-dependent errors occur
/
the bus interface should not perform the remote bus write-access or abort it if the
remote bus supports aborted cycles. In this case the failure of the stwcx instruc-
tion is reported to the RCPU.
MPC556
9-32, the same situation is shown except that the MPC555 / MPC556 is
illustrates the behavior of the MPC555 / MPC556 when the RETRY signal
EXTERNAL BUS INTERFACE
Rev. 15 October 2000
MOTOROLA
9-43