MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 547

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MIOS1LVL0 — MIOS1 Interrupt Level Register 0
15.8.2.2 MIOS1 Interrupt Level Register 1 (MIOS1LVL1)
MIOS1LVL1 — MIOS1 Interrupt Level 1 Register
15.8.3 Interrupt Control Section (ICS)
MPC555
USER’S MANUAL
MSB
MSB
Bit(s)
10:15
Bit(s)
10:15
0:4
5:7
8:9
0:4
5:7
8:9
0
0
0
0
RESET:
RESET:
This register contains the interrupt level that applies to the submodules number 31 to
16.
The interrupt control section delivers the interrupt level to the CPU. The interrupt con-
trol section adapts the characteristics of the MIOB request bus to the characteristics
of the interrupt structure of the IMB3.
When at least one of the flags is set on an enabled level, the ICS receives a signal
from the corresponding IRQ pending register. This signal is the result of a logical “OR”
between all the bits of the IRQ pending register.
The signal received from the IRQ pending register is associated with the interrupt level
register within the ICS. This level is coded on five bits in this register: three bits repre-
sent one of eight levels and the two other represent the four time multiplex slots. Ac-
1
0
—
LVL
TM
—
1
0
/
MPC556
RESERVED
RESERVED
Name
Name
LVL
TM
—
—
2
0
2
0
Reserved
Interrupt request level. This field represents one of eight possible levels.
Time multiplexing. This field determines the multiplexed time slot
Reserved
Reserved
Interrupt request level. This field represents one of eight possible levels.
Time multiplexing. This field determines the multiplexed time slot.
Reserved
3
0
3
0
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Table 15-7 MIOS1LVL0 Bit Descriptions
Table 15-8 MIOS1LVL1 Bit Descriptions
4
0
4
0
5
0
5
0
LVL
LVL
Rev. 15 October 2000
6
0
6
0
7
0
7
0
8
0
8
0
Description
Description
TM
TM
9
0
9
0
10
10
0
0
11
11
0
0
RESERVED
RESERVED
12
12
0
0
13
13
0
0
0x30 6C30
0x30 6C70
MOTOROLA
14
14
0
0
15-11
LSB
LSB
15
15
0
0