MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 247

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.1 Reset Operation
7.1.1 Power On Reset
MPC555 / MPC556
USER’S MANUAL
This section describes the MPC555 / MPC556 reset sources, operation, control, and
status.
The MPC555 / MPC556 has several inputs to the reset logic which include the follow-
ing:
All of these reset sources are fed into the reset controller. The control logic determines
the cause of the reset, synchronizes it if necessary, and resets the appropriate logic
modules, depending on the source of the reset. The memory controller, system pro-
tection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
External soft reset initializes internal logic while maintaining system configuration.
The reset status register (RSR) reflects the most recent source to cause a reset.
down low-power mode, this pin should be activated only as a result of a voltage failure
in the KAPWR pin. After detecting the assertion of PORESET, the MPC555 / MPC556
enters the power-on reset state. During this state the MODCK[1:3] signals determine
the oscillator frequency, PLL multiplication factor, and the PITRCLK and TMBCLK
clock sources. In addition, the MPC555 / MPC556 asserts the SRESET and HRESET
pins.
The PORESET pin should be asserted for a minimum time of 100,000 cycles of clock
oscillator after a valid level has been reached on the KAPWR supply. After detecting
the assertion of PORESET, the MPC555 / MPC556 remains in the power-on reset
state until the last of the following two events occurs:
The power-on reset pin, PORESET, is an active low input. In a system with power-
• Power on reset
• External hard reset pin (HRESET)
• External soft reset pin (SRESET)
• Loss of lock
• On-chip clock switch
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
• Debug port soft reset
• JTAG reset
• The Internal PLL enters the lock state and the system clock is active.
• The PORESET pin is negated.
Rev. 15 October 2000
SECTION 7
RESET
RESET
MOTOROLA
7-1