MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 134

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

GPRs — General-Purpose Registers
FPRs— Floating-Point Registers
MSB
MSB
3.7.1 General-Purpose Registers (GPRs)
3.7.2 Floating-Point Registers (FPRs)
3.7.3 Floating-Point Status and Control Register (FPSCR)
MPC555
USER’S MANUAL
0
0
Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below.
These registers are accessed as source and destination registers through operands
in the instruction syntax.
The PowerPC architecture provides thirty-two 64-bit FPRs. These registers are ac-
cessed as source and destination registers through operands in floating-point instruc-
tions. Each FPR supports the double-precision, floating-point format. Every instruction
that interprets the contents of an FPR as a floating-point value uses the double-preci-
sion floating-point format for this interpretation. That is, all floating-point numbers are
stored in double-precision format.
All floating-point arithmetic instructions operate on data located in FPRs and, with the
exception of the compare instructions (which update the CR), place the result into an
FPR. Information about the status of floating-point operations is placed into the float-
ing-point status and control register (FPSCR) and in some cases, into the CR, after the
completion of the operation’s writeback stage. For information on how the CR is affect-
ed by floating-point operations, see
The FPSCR controls the handling of floating-point exceptions and records status re-
sulting from the floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31]
are control bits.
1
2
/
3
MPC556
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
RESET: UNCHANGED
RESET: UNCHANGED
3.7.4 Condition Register
GPR31
FPR31
GPR0
GPR1
FPR0
FPR1
. . .
. . .
. . .
. . .
(CR).
MOTOROLA
3-12
LSB
LSB
31
63