MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 724

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
• NMI exception as a result of the assertion of the IRQ0_B pin. For more information
• Check stop. Refer to
• Machine check exception
• Implementation specific instruction protection error
• Implementation specific data protection error
• External interrupt, recognized when MSREE = 1
• Alignment interrupt
• Program interrupt
• Floating point unavailable exception
• Floating point assist exception
• Decrementer exception, recognized when MSREE = 1
• System call exception
• Trace, asserted when in single trace mode or when in branch trace mode (refer to
• Implementation dependent software emulation exception
• Instruction breakpoint, when breakpoints are masked (BRKNOMSK bit in the
• Load/store breakpoint, when breakpoints are masked (BRKNOMSK bit in the
• Peripherals breakpoint, from the development port, internal and external modules.
• Development port non-maskable interrupt, as a result of a debug station request.
The internal freeze signal is asserted whenever an enabled event occurs, regardless
if debug mode is enabled or disabled. The internal freeze signal is connected to all rel-
evant internal modules. These modules can be programmed to stop all operations in
response to the assertion of the freeze signal. Refer to
The freeze indication is negated when exiting debug mode. Refer to
Debug Mode
The following list contains the events that can cause the CPU to enter debug mode.
Each event results in debug mode entry if debug mode is enabled and the correspond-
ing enable bit is set. The reset values of the enable bits let the user, in most cases, to
use of the debug mode features without the need to program the debug enable register
(DER). For more information refer to
refer to
3.15.4.10 Trace
LCTRL2 is clear) recognized only when MSRRI = 1, when breakpoints are not
masked (BRKNOMSK bit in the LCTRL2 is set) always recognized
LCTRL2 is cleared) recognized only when MSRRI = 1, when breakpoints are not
masked (BRKNOMSK bit in the LCTRL2 is set) always recognized
are recognized only when MSRRI = 1.
Useful in some catastrophic events like an endless loop when MSRRI = 0. As a result
of this event the machine may enter a non-restartable state, for more information re-
fer to
/
MPC556
3.15.4
3.15.4.1 System Reset Interrupt
Interrupts.
Interrupt)
21.4.1.3 The Check Stop State and Debug Mode
DEVELOPMENT SUPPORT
Rev. 15 October 2000
21.7.12 Debug Enable Register
21.6.1 Freeze
21.4.1.6 Exiting
Indication.
(DER).
MOTOROLA
21-28