MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 444

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
The QADC64 has three global registers for configuring module operation: the module
configuration register (QADC64MCR), the interrupt register (QADC64INT), and a test
register (QADC64TEST). The global registers are always defined to be in supervisor
data space. The CPU allows software to establish the global registers in supervisor
data space and the remaining registers and tables in user space.
/
NOTES:
Access
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. S = Supervisor only
2. Access is restricted to supervisor only and factory test mode only.
3. S/U = Unrestricted or supervisor depending on the state of the SUPV bit in the QADC64MCR.
S
T
---
S
1
2
3
0x30 4C14 – 0x30 4DFE
0x30 4A80 – 0x30 4AFE
0x30 4E80 – 0x30 4EFE
0x30 4B80 – 0x30 4BFE
0x30 4A00 – 0x30 4A7E
0x30 4E00 – 0x30 4E7E
0x30 4B00 – 0x30 4B7E
0x30 4F80 – 0x30 4FFE
0x30 4814 – 0x30 49FE
0x30 4F00 – 0x30 4F7E
0x30 4C0A
0x30 4C0C
0x30 4C0E
0x30 4810,
0x30 4812,
0x30 4C00
0x30 4C02
0x30 4C04
0x30 4C06
0x30 4C08
0x30 480A
0x30 480C
0x30 480E
0x30 4C10
0x30 4C12
0x30 4800
0x30 4802
0x30 4804
0x30 4806
0x30 4808
Table 13-6 QADC64 Address Map
Address
Rev. 15 October 2000
MSB
0
Left-Justified, Signed Result Register (LJSRR_x)
See
Conversion Command Word (CCW_x) Table
Port A Data Direction Register (DDRQA_x)
QADC64 Test Register (QADC64TEST_x)
Right-Justified, Unsigned Result Register
QADC64 Module Configuration Register
QADC64 Control Register 0 (QACR0_x)
QADC64 Control Register 1 (QACR1_x)
QADC64 Control Register 2 (QACR2_x)
Left-Justified, Unsigned Result Register
Table 13-10
QADC64 Status Register 0 (QASR0_x)
QADC64 Status Register 1 (QASR1_x)
(PORTQA_x)
descriptions.
Port A Data
See
See
See
See
See
See
See
See
See
Interrupt Register (QADC64INT_x)
See
See
See
Table 13-10
Table 13-11
Table 13-12
Table 13-14
Table 13-16
Table 13-18
Table 13-19
Table 13-7
Table 13-8
13.12.12
13.12.12
13.12.12
Result Word Table
Result Word Table
Result Word Table
(QADC64MCR_x)
for bit
(RJURR_x)
(LJURR_x)
Reserved
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
(PORTQB_x)
Port B Data
LSB
MOTOROLA
15
13-32