MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 174

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.15.4.16 Partially Executed Instructions
MPC555
USER’S MANUAL
For L-bus breakpoint instances, these registers are set to:
Execution resumes at offset from the base address indicated by MSR
In general, the architecture permits instructions to be partially executed when an align-
ment or data storage interrupt occurs. In the core, instructions are not executed at all
if an alignment interrupt condition is detected and data storage interrupt is never gen-
erated by the hardware. In the MPC555 / MPC556, the instruction can be partially ex-
ecuted only in the case of the load/store instructions that cause multiple access to the
memory subsystem. These instructions are:
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
• 0x01D00 – For instruction breakpoint match
• 0x01C00 – For data breakpoint match
• 0x01E00 – For development port maskable request or a peripheral breakpoint
• 0x01F00 – For development port non-maskable request
/
MPC556
DAR and DSISR
Register Name
Register Name
BAR
CENTRAL PROCESSING UNIT
10:15
Other
Other
Bits
Bits
ME
1:4
LE
IP
Rev. 15 October 2000
For I-breakpoints, set to the effective address of the instruc-
tion that caused the interrupt. For L-breakpoint, set to the ef-
fective address of the instruction following the instruction that
caused the interrupt. For development port maskable request
or a peripheral breakpoint, set to the effective address of the
instruction that the processor would have executed next if no
interrupt conditions were present. If the development port re-
quest is asserted at reset, the value of SRR0 is undefined.
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
If the development port request is asserted at reset, the value
of SRR1 is undefined.
No change
No change
Bit is copied from ILE
Set to 0
Set to the effective address of the data access as computed
by the instruction that caused the interrupt
Do not change
RI
.
Description
Description
IP
as follows:
MOTOROLA
3-52