MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 448

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

QACR1 — Control Register 1
13.12.7 QADC64 Control Register 1 (QACR1)
RESET:
MPC555
USER’S MANUAL
Bit(s)
13:15
MSB
CIE1
7:11
1:2
4:6
12
0
0
0
3
Control register 1 is the mode control register for the operation of queue 1. The appli-
cations software defines the queue operating mode for the queue, and may enable a
completion and/or pause interrupt. All of the control register fields are read/write data.
However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of
the bits are typically written once when the software initializes the QADC64, and not
changed afterwards.
PIE1
/
1
0
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Name
MUX
TRG
PSH
PSA
PSL
—
—
SSE1
2
0
Externally multiplexed mode. The MUX bit configures the QADC64 for externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[2:0] pins to be
outputs.
0 = Internally multiplexed, 16 possible channels
1 = Externally multiplexed, 41 possible channels
Reserved
Trigger assignment. TRG allows the software to assign the ETRIG[2:1] pins to queue 1 and
queue 2.
0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2
1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1
Reserved
Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value
plus 1 represents the high time in IMB clocks
Note that this bit location is maintained for software compatibility with previous versions of the
QADC64. It serves no functional benefit in the MPC555 / MPC556 and is not operational.
Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value
plus 1 represents the low time in IMB clocks
3
0
Table 13-11 QACR0 Bit Descriptions
4
0
MQ1
5
0
Rev. 15 October 2000
6
0
7
0
8
0
Description
9
0
10
0
RESERVED
11
0
12
0
13
0
0x30 4C0C
0x30 480C
MOTOROLA
14
0
13-36
LSB
15
0