MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 484

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.2.1 Receive RAM
14.7.2.2 Transmit RAM
14.7.2.3 Command RAM
MPC555
USER’S MANUAL
Data received by the QSPI is stored in this segment, to be read by the CPU. Data
stored in the receive RAM is right-justified,( i.e., the least significant bit is always in the
right-most bit position within the word regardless of the serial transfer length). Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. The CPU can access the data using byte, half-word, or word ad-
dressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed. If
the corresponding peripheral, such as a serial input port, is used solely to input data,
then this segment does not need to be initialized.
Data must be written to transmit RAM in a right-justified format. The QSPI cannot mod-
ify information in the transmit RAM. The QSPI copies the information to its data serial-
izer for transmission. Information remains in transmit RAM until overwritten.
Command RAM is used by the QSPI in master mode. The CPU writes one byte of con-
trol information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 32 bytes. Each byte is divided into two fields. The periph-
eral chip-select field, enables peripherals for transfer. The command control field pro-
vides transfer options.
0x30 517F
0x30 5140
/
MPC556
Half-Word
Receive
RAM
RRD
RRE
RRF
RR1
RR2
RR0
QUEUED SERIAL MULTI-CHANNEL MODULE
Figure 14-5 QSPI RAM
0x30 51BF
0x30 5180
Rev. 15 October 2000
Half-Word
Transmit
RAM
TRD
TRE
TRF
TR0
TR1
TR2
0x30 51C0
0x30 51DF
Command
RAM
CRD
CRE
CRF
CR0
CR1
CR2
Byte
MOTOROLA
14-22