MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 438

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
(FROM CONTROL REGISTER 0):
PRESCALER RATE SELECTION
IMB CLOCK (F
To accommodate wide variations of the main MCU clock frequency (IMB clock —
F
clock to a frequency within the specified QCLK tolerance range. To allow the A/D con-
version time to be maximized across the spectrum of IMB clock frequencies, the
QADC64 prescaler permits the frequency of QCLK to be software selectable. It also
allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH
(prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK
with the prescaler clock low time (PSL) field. The combination of the PSH and PSL pa-
rameters establishes the frequency of the QCLK.
SYS
Queue 1 & 2 TIMER MODE RATE SELECTION
HIGH TIME CYCLES (PSH)
LOW TIME CYCLES (PSL)
ADD HALF CYCLE TO HIGH (PSA)
INPUT SAMPLE TIME (FROM CCW)
/
), QCLK is generated by a programmable prescaler which divides the MCU IMB
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
SYS
)
Figure 13-8 QADC64 Clock Subsystem Functions
5
DOWN COUNTER
8
ONE'S COMPLEMENT
5-BIT
COMPARE
2
3
DETECT
ZERO
5
3
Rev. 15 October 2000
2 7
2 8
LOAD PSH
2 9
2 10
PERIODIC/INTERVAL
BINARY COUNTER
A/D CONVERTER
STATE MACHINE
TIMER SELECT
2 11
2 12
2 13
2 14
RESET QCLK
SET QCLK
2 15
2 16 2 17
( F
GENERATE
SYS
QADC64 CLOCK
CLOCK
10
/ ÷2 TO F
2
SYS
/÷40 )
SAR CONTROL
SAR
PERIODIC/INTERVAL
TRIGGER EVENT
FOR Q1 AND Q2
QCLK
MOTOROLA
13-26