MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 482

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.1.5 QSPI Status Register
SPSR — QSPI Status Register
MPC555
USER’S MANUAL
Bit(s)
MSB
8:15
0:4
0
5
6
7
The SPSR contains information concerning the current serial transmission. Only the
QSPI can set bits in this register. To clear status flags, the CPU reads SPSR with the
flags set and then writes the SPSR with zeros in the appropriate bits. Writes to CPTQP
have no effect.
*See bit descriptions in
1
/
LOOPQ
MPC556
Name
HALT
HMIE
—
—
2
Reserved
QSPI loop mode. LOOPQ controls feedback on the data serializer for testing.
0 = Feedback path disabled.
1 = Feedback path enabled.
HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA
status flag or the MODF status flag in SPSR.
0 = HALTA and MODF interrupts disabled.
1 = HALTA and MODF interrupts enabled.
from which it can later be restarted. Refer to
0 = QSPI operates normally.
1 = QSPI is halted for subsequent restart.
SPSR.
Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
3
SPCR3*
Table
SeeTable 14-18
QUEUED SERIAL MULTI-CHANNEL MODULE
4
Table 14-17 SPCR3 Bit Descriptions
14-17.
5
Rev. 15 October 2000
for bit descriptions.
6
7
SPIF
8
0
Description
14.7.4.1 Enabling, Disabling, and Halting the
MODF
9
0
HAL-
TA
10
0
11
0
12
0
CPTQP
13
0
0x30 501E
MOTOROLA
14
0
14-20
LSB
15
SPI.
0