MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 291

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.12.2 PLL, Low-Power, and Reset-Control Register (PLPRCR)
MPC555
USER’S MANUAL
Bit(s)
25:27
29:31
24
28
The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered
by the keep alive power supply.
/
MPC556
Name
DFNH
DFNL
—
—
Table 8-9 SCCR Bit Descriptions (Continued)
Reserved
Division factor low frequency. The user can load these bits with the desired divide value and
the CSRC bit to change the frequency. Changing the value of these bits does not result in a
loss of lock condition. These bits are cleared by power-on or hard reset. Refer to
eral System Clocks
000 = Divide by 2
001 = Divide by 4
010 = Divide by 8
011 = Divide by 16
100 = Divide by 32
101 = Divide by 64
110 = Reserved
111 = Divide by 256
Reserved
Division factor high frequency. These bits determine the general system clock frequency dur-
ing normal mode. Changing the value of these bits does not result in a loss of lock condition.
These bits are cleared by power-on or hard reset. The user can load these bits at any time
to change the general system clock rate. Note that the GCLKs generated by this division fac-
tor are not 50% duty cycle (i.e. CLKOUT).
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Reserved
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
and
Figure 8-5
for details on using these bits.
Description
MOTOROLA
8.6.1 Gen-
8-31