MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 32

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Number
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
11-1
11-2
11-3
12-1
12-2
12-3
12-4
12-5
12-6
13-1
13-2
13-3
13-4
13-5
13-6
MPC555 / MPC555
USER’S MANUAL
Figure
Memory Controller Function Within the USIU ............................................... 10-1
Memory Controller Block Diagram ................................................................ 10-2
MPC555 / MPC556 Simple System Configuration ....................................... 10-3
Bank Base Address and Match Structure ..................................................... 10-4
MPC555 / MPC556 GPCM–Memory Devices Interface ............................... 10-7
Memory Devices Interface Basic Timing
Peripheral Devices Interface ........................................................................ 10-9
Peripheral Devices Basic Timing
Relaxed Timing–Read Access
Relaxed Timing–Write Access
Relaxed Timing–Write Access
Relaxed Timing–Write Access
Consecutive Accesses (Write After Read, EHTR = 0) ................................ 10-15
Consecutive Accesses (Write After Read, EHTR = 1) ................................ 10-16
Consecutive Accesses
Consecutive Accesses
Aliasing Phenomena Illustration ................................................................. 10-23
Synchronous External Master
Synchronous External Master Basic Access (GPCM Controlled) .............. 10-26
L2U Bus Interface Block Diagram ................................................................ 11-2
DMP Basic Functional Diagram .................................................................... 11-4
Region Base Address Example .................................................................... 11-6
UIMB Interface Module Block Diagram ........................................................ 12-2
IMB Clock – Full-Speed IMB Bus ................................................................. 12-3
IMB Clock – Half-Speed IMB Bus ................................................................. 12-3
Interrupt Synchronizer Signal Flow ............................................................... 12-4
Time-Multiplexing Protocol for IRQ pins ....................................................... 12-5
Interrupt Synchronizer Block diagram .......................................................... 12-6
QADC64 Block Diagram ............................................................................... 13-1
QADC64 Input and Output Signals ............................................................... 13-3
Example of External Multiplexing ............................................................... 13-10
QADC64 Module Block Diagram ................................................................ 13-12
Conversion Timing ...................................................................................... 13-13
Bypass Mode Conversion Timing ............................................................... 13-13
(ACS = 00,TRLX = 0) ................................................................................ 10-8
(ACS = 11,TRLX = 0) ................................................................................ 10-9
(ACS = 11, SCY = 1, TRLX = 1) ............................................................. 10-11
(ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ........................................... 10-12
(ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ........................................... 10-13
(ACS = 00, SCY = 0, CSNT = 1, TRLX = 1 ............................................. 10-14
(Read After Read From Different Banks, EHTR = 1) .............................. 10-17
(Read After Read From Same Bank, EHTR = 1) .................................... 10-18
Configuration For GPCM–Handled Memory Devices ............................. 10-25
Rev. 15 October 2000
LIST OF FIGURES
MOTOROLA
Number
Page
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