MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 297

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.1 Features
9.2 Bus Transfer Signals
MPC555 / MPC556
USER’S MANUAL
The MPC555 / MPC556 bus is a synchronous, burstable bus. Signals driven on this
bus are required to make the setup and hold time relative to the bus clock’s rising
edge. The bus has the ability to support multiple masters. The MPC555 / MPC556 ar-
chitecture supports byte, half-word, and word operands allowing access to 8-, 16-, and
32-bit data ports through the use of synchronous cycles controlled by the size outputs
(TSIZ0, TSIZ1). For accesses to 16- and 8-bit ports, the slave must be controlled by
the memory controller.
The external bus interface features are listed below.
The bus transfers information between the MPC555 / MPC556 and external memory
of a peripheral device. External devices can accept or provide 8, 16, and 32 bits in par-
allel and must follow the handshake protocol described in this section. The maximum
number of bits accepted or provided during a bus transfer is defined as the port width.
The MPC555 / MPC556 contains an address bus that specifies the address for the
transfer and a data bus that transfers the data. Control signals indicate the beginning
and type of the cycle, as well as the address space and size of the transfer. The se-
lected device then controls the length of the cycle with the signal(s) used to terminate
the cycle. A strobe signal for the address bus indicates the validity of the address and
provides timing information for the data.
• 32-bit address bus with transfer size indication (only 24 available on pins)
• 32-bit data bus
• Bus arbitration logic on-chip supports an external master
• Internal chip-select and wait state generation to support peripheral or static mem-
• Supports various memory (SRAM, EEPROM) types: synchronous and asynchro-
• Supports non-wrap bursts
• Flash ROM programming support
• Compatible with PowerPC architecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
• Bus can operate at the same frequency as the MPC555 / MPC556 or half the fre-
ory devices through the memory controller
nous, burstable and non-burstable
quency.
EXTERNAL BUS INTERFACE
EXTERNAL BUS INTERFACE
Rev. 15 October 2000
SECTION 9
MOTOROLA
9-1