MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 409

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UMCR — UIMB Module Configuration Register
12.5 Programming Model
12.5.1 UIMB Module Configuration Register (UMCR)
MPC555
USER’S MANUAL
STOP
MSB
HRESET:
0
0
16
HRESET:
0
Table 12-5
address offset shown in this table is from the start of the block reserved for UIMB reg-
isters. As shown in
gins at offset 0x30 7F80 from the start of the MPC555 / MPC556 internal memory map
(the last 128-byte sub-block of the UIMB interface memory map).
Any word, half-word or byte access to a 32-bit location within the UIMB interface reg-
ister decode block that is unimplemented (defined as reserved) causes the UIMB in-
terface to asserting a data error exception on the U-bus.The entire 32-bit location must
be defined as reserved in order for a data error exception to be asserted.
Unimplemented bits in a register return zero when read.
The UIMB module configuration register (UMCR) is accessible in supervisor mode
only.
1
0
IRQMUX
17
/
0
MPC556
NOTES:
Access
S/T
1. S = Supervisor mode only, T = Test mode only
S
—
—
2
0
S
18
0
1
lists the registers used for configuring and testing the UIMB module. The
HSPEE
19
0x30 7F80
0x30 7F84 —
0x30 7F8C
0x30 7F90
0x30 7F94 —
0x30 7F9C
0x30 7FA0
D
3
1
0
Figure 1-3
Base Address
Table 12-5 UIMB Interface Register Map
20
0
4
0
U-BUS TO IMB3 BUS INTERFACE (UIMB)
21
0
5
0
in
Rev. 15 October 2000
22
0
1.3 MPC555 / MPC556 Address
6
0
UIMB Module Configuration Register (UMCR)
See
Reserved
UIMB Test Control Register (UTSTCREG)
Reserved
Reserved
Interrupt Request Pending (UIPEND)
See
(UIPEND)
RESERVED
23
0
7
0
Table 12-6
12.5.3 Pending Interrupt Request Register
24
0
8
0
for bit descriptions.
for bit descriptions.
RESERVED
25
0
9
0
Register
26
0
10
0
27
0
11
0
28
0
12
0
Map, this block be-
29
0
13
0
0x30 7F80
MOTOROLA
30
0
14
0
LSB
31
12-7
0
15
0