MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 252

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.5 Reset Configuration
7.5.1 Hard Reset Configuration
MPC555
USER’S MANUAL
Bit(s)
NOTES:
13:15
10
11
12
9
1. In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
When a hard reset event occurs, the MPC555 / MPC556 reconfigures its hardware
system as well as the development port configuration The logical value of the bits that
determine its initial mode of operation, are sampled from the following:
If at the sampling time (at HRESET negation) RSTCONF is asserted, then the config-
uration is sampled from the data bus. If RSTCONF is negated and a valid NVM value
exists (CMFCFIG bit HC=0), then the configuration is sampled from the NVM register
in the CMF module. If RSTCONF is negated and no valid NVM value exists (CMFCFIG
bit HC=1), then the configuration word is sampled from the internal default. HC will be
“1” if the internal flash is erased.
tions.
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
• The external data bus pins DATA[0:31]
• An internal default constant (0x0000 0000)
• An internal NVM register value (CMFCFIG)
/
GHRST
GSRST
GPOR
MPC556
Name
ILBC
—
Table 7-3 Reset Status Register Bit Descriptions (Continued)
If the CMFCFIG reset config word is being used, then the flash is au-
tomatically enabled.
Illegal bit change. This bit is set when the MPC555 / MPC556 changes any of the following bits
when they are locked:
LPM[0:1], locked by the LPML bit
MF[0:11], locked by the MFPDL bit
DIVF[0:4], locked by the MFPDL bit
Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more
than TBD ns
0 = No glitch was detected on the PORESET pin
1 = A glitch was detected on the PORESET pin
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
TBD ns
0 = No glitch was detected on the HRESET pin
1 = A glitch was detected on the HRESET pin
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than TBD ns the GHRST
bit will be set. If an internal or external SRESET is generated the SRESET pin is asserted and
the GSRST bit will be set. The GSRST bit remains set until software clears it. The GSRST bit
can be negated by writing a one to GSRST. A write of zero has no effect on this bit.
0 = No glitch was detected on SRESET pin
1 = A glitch was detected on SRESET pin
Reserved
Rev. 15 October 2000
Table 7-4
RESET
NOTE
Description
.
summarizes the reset configuration op-
MOTOROLA
7-6