MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 986
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
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READI Module
24.6.2
The control and status information is accessed via the four auxiliary access public messages: device ready
for upload/download, upload request (tool requests information), download request (tool provides
information), and upload/download information (device/tool provides information).
To write control or status to memory-mapped locations the following sequence would be required.
24-18
1
1. The tool confirms that the device is ready (so as to not cancel an ongoing read write access). The
2. The tool waits for device ready for upload/download (TCODE 16) message before initiating next
RCPU
23:45
46:47
Bits
Data trace range start and end addresses must be word-aligned.
tool transmits the download request public message (TCODE 18) which contains write attributes,
write data, and target address.
access.
Accessing Memory-Mapped Locations Via
the Auxiliary Port
Nexus
Bits
24:2
1:0
There is no way to distinguish between off-core MPC500 special purpose
register (SPR) map and normal memory map accesses via the defined
address range control. If data trace ranges are set up such that the off-core
MPC500 SPR map falls within active ranges, then accesses to these off-core
MPC500 SPRs will be traced, and the messages will not be distinguishable
from accesses to normal memory map space. Off-core MPC500 SPRs
typically exist in the 8- to 16-Kbyte lowest memory block (0x2000 –
0x3FF0). If data or peripherals are mapped to this space, load/stores to
MPC500 SPRs will be indistinguishable from data or peripheral accesses.
Programmed Values
DTSA
Name
DTSA < DTEA
DTSA > DTEA
DTSA = DTEA
TA
Table 24-15. DTA 1 AND 2 Bit Descriptions (continued)
1
The Read/Write Start Field defines the starting address for the address range.
Refer to
The Read/Write Trace Field can be configured to allow enabling or disabling data read
and/or data write traces.
00 Disable data read and data write trace
x1 Enable data read trace
1x Enable data write trace
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-16. Data Trace Values
Table
24-16.
NOTE
DTSA
Range Selected
Word at DTSA
→
Invalid Range
Description
←
DTEA
Freescale Semiconductor
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