MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 102

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
2-4
TEA
OE
RSTCONF / TEXP
BI / STS
Signal Name
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
O
O
O
I
TEA
OE
RSTCONF until
reset negates.
Controlled by
RCW[DBGC].
See
Function after
Reset
Table
6-8.
1
Transfer Error Acknowledge. This signal indicates that a bus
error occurred in the current transaction. The
MPC561/MPC563 asserts this signal when the bus monitor
does not detect a bus cycle termination within 2040 clock
cycles. The assertion of TEA causes the termination of the
current bus cycle, regardless of the state of TA.
An external pull-up device is required to negate TEA quickly,
before a second error is detected. That is, the signal must
be pulled up within one clock cycle of the time it was
three-stated by the MPC561/MPC563.
Output Enable. This output line is asserted when a read
access is initiated by the MPC561/MPC563 to an external
slave controlled by the memory controller’s GPCM.
Reset Configuration. This input line is sampled by the
MPC561/MPC563 during the assertion of the HRESET
signal in order to sample the reset configuration. If the line
is asserted, the configuration mode is sampled from the
external data bus. When this line is negated, the
configuration mode adopted by the MPC561/MPC563 is
either the internal default or read from the internal Flash
(MPC563 only).
Timer Expired. This output line reflects the status of
PLPRCR[TEXPS] in the USIU. This bit indicates an expired
timer value.
Burst Inhibit. This bidirectional, active-low, three-state
signal indicates that the slave device addressed in the
current burst transaction is not able to support burst
transfers. When the MPC561/MPC563 drives out the signal
for a specific transaction, it asserts or negates BI according
to the value specified in the appropriate control registers.
The signal is negated after the end of the transaction and
then is immediately three-stated.
This is an active-low signal and needs an external pull-up
resistor to ensure proper operation and signal timing
specifications.
Special Transfer Start. This output signal is driven by the
MPC561/MPC563 to indicate the start of a transaction on
the external bus or signals the beginning of an internal
transaction in show cycle mode.
Description
Freescale Semiconductor