MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 186

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
3.13.10 Load/Store Processor
The load/store processor supports all of the 32-bit implementation fixed-point PowerPC ISA load/store
instructions in the hardware.
3.13.10.1 Fixed-Point Load with Update and Store with Update Instructions
For load with update and store with update instructions, when rA = 0, the EA is written into R0. For load
with update instructions, when rA = rD, rA is boundedly undefined.
3.13.10.2 Fixed-Point Load and Store Multiple Instructions
For these types of instructions, EA must be a multiple of four. If it is not, the system alignment error
handler is invoked. For a lmw instruction (if rA is in the range of registers to be loaded), the instruction
completes normally. rA is then loaded from the memory location as follows:
rA ← MEM(EA+(rA-rD)*4, 4)
3.13.10.3 Fixed-Point Load String Instructions
Load string instructions behave the same as load multiple instructions, with respect to invalid format in
which rA is in the range of registers to be loaded. When rA is in range, it is updated from memory.
3.13.10.4 Storage Synchronization Instructions
For these type of instructions, EA must be a multiple of four. If it is not, the system alignment error handler
is invoked.
3.13.10.5 Floating-Point Load and Store With Update Instructions
For Load and Store with update instructions, if rD = 0 then the EA is written into R0.
3.13.10.6 Floating-Point Load Single Instructions
When the operand falls in the range of a single denormalized number, the floating-point assist interrupt
handler is invoked.
Refer to the RCPU Reference Manual (Floating-point Assist For Denormalized Operands) for complete
description of handling denormalized floating-point numbers.
3.13.10.7 Floating-Point Store Single Instructions
When the operand falls in the range of a single denormalized number, the floating-point assist interrupt
handler is invoked.
When the operand is ZERO it is converted to the correct signed ZERO in single-precision format.
When the operand is between the range of single denormalized and double denormalized it is considered
a programming error. The hardware will handle this case as if the operand was single denormalized.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-42
Freescale Semiconductor