MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 730

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
16.7.14 Interrupt Flag Register (IFLAG)
16.7.15 Error Counters (RXECTR, TXECTR)
16-36
SRESET
SRESET
Bits
8:15
Bits
8:15
Bits
8:15
0:7,
0:7,
0:7,
Field
Addr
Field
Addr
Figure 16-22. Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR)
MSB
MSB
RXECTR,
0
0
IMASKH,
TXECTR
IFLAGH,
IMASKL
IFLAGL
Name
Name
Name
1
1
0x30 70A6 (RxECTR_A/TxECTR_A); 0x30 74A6 (RxECTR_B/TxECTR_B); 0x30 78A6
IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with a 16-bit
read or write, and IMASKH and IMASKL can be accessed with byte reads or writes.
IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which
buffers will generate interrupts after successful transmission/reception. Setting a bit in
IMASK enables interrupt requests for the corresponding message buffer.
IFLAG contains two 8-bit fields, IFLAGH and IFLAGL. IFLAG can be accessed with a 16-bit
read or write, and IFLAGH and IFLAGL can be accessed with byte reads or writes.
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets
the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request
will be generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a
new flag setting event occur between the time that the CPU reads the flag as a one and
writes the flag as a zero, the flag is not cleared. This register can be written to zeros only.
Both counters are read only, except when the TouCAN is in test or debug mode.
2
2
0x30 70A4 (IFLAG_A); 0x30 74A4 (IFLAG_B); 0x30 78A4 (IFLAG_C)
Table 16-28. RXECTR, TXECTR Bit Descriptions
RXECTR
Figure 16-21. Interrupt Flag Register (IFLAG)
IFLAGH
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-26. IMASK Bit Descriptions
Table 16-27. IFLAG Bit Descriptions
4
4
5
5
(TxECTR_C/TxECTR_C)
0000_0000_0000_0000
0000_0000_0000_0000
6
6
7
7
Description
Description
Description
8
8
9
9
10
10
TXECTR
11
11
IFLAGL
12
12
Freescale Semiconductor
13
13
14
14
LSB
LSB
15
15