MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 321

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

8.7.3.2
The system changes from doze mode to normal-high mode whenever an interrupt is pending from the
interrupt controller.
8.7.3.3
The system switches from deep-sleep mode to normal-high mode if any of the following conditions is met:
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500 PLL input
frequency clocks. In one-to-one mode the wake-up time may be up to 100 PLL input frequency clocks.
For a PLL input frequency of 4 MHz, the wake-up time is less than 125 µs.
8.7.3.4
Exit from power-down mode is accomplished through hard reset. External logic should assert HRESET in
response to the TEXPS bit being set and TEXP pin being asserted. The TEXPS bit is set by an enabled
RTC, PIT, time base, or decrementer interrupt. The hard reset should be asserted for no longer than the
time it takes for the power supply to wake-up in addition to the PLL lock time. When the TEXPS bit is
cleared (and the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be asserted,
and causes an exit from power-down low-power mode. Refer to
more information.
8.7.3.5
Figure 8-9
Freescale Semiconductor
•
•
•
An interrupt is pending from the interrupt controller
An interrupt is requested by the RTC, PIT, or time base
A decrementer exception
shows the flow among the different power modes.
Exiting from Doze Mode
Exiting from Deep-Sleep Mode
Exiting from Power-Down Mode
Low-Power Modes Flow
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 8.8.3, “Keep-Alive
Clocks and Power Control
Power” for
8-19