MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 184

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
3.13.3
Non-optional instructions are implemented by the hardware. Optional instructions are executed by
implementation-dependent code and any attempt to execute one of these commands causes the RCPU to
take the implementation-dependent software emulation interrupt (offset 0x01000 of the vector table).
Illegal and reserved instruction class instructions are supported by implementation- dependent code and,
thus, the RCPU hardware generates the implementation-dependent software emulation interrupt. Invalid
and preferred instruction forms treatment by the RCPU is described under the specific processor
compliance sections.
3.13.4
Invocation of the system software for any instruction-caused exception in the RCPU is precise, regardless
of the type and setting.
3.13.5
The RCPU implements all the instructions defined for the branch processor in the UISA in the hardware.
3.13.6
The core fetches a number of instructions into its internal buffer (the instruction pre-fetch queue) prior to
execution. If a program modifies the instructions it intends to execute, it should call a system library
program to ensure that the modifications have been made visible to the instruction fetching mechanism
prior to execution of the modified instructions.
3.13.7
The core implements all the instructions defined for the branch processor by the UISA in the hardware.
For performance of various instructions, refer to
3.13.7.1
Bits marked with z in the BO encoding definition are discarded by the MPC561/MPC563 decoding. Thus,
these types of invalid form instructions yield results of the defined instructions with the z-bit zero. If the
decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address of the
branch is the new value of the CTR. Condition is evaluated correctly, including the value of the counter
after decrement.
3.13.7.2
The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-ready branch
conditions. No prediction is done for branches to the link or count register if the target address is not ready.
Refer to the RCPU Reference Manual (conditional branch control) for more information.
3-40
Classes of Instructions
Exceptions
Branch Processor
Instruction Fetching
Branch Instructions
Invalid Branch Instruction Forms
Branch Prediction
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-20
of this manual.
Freescale Semiconductor