MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 884

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CDR3 Flash (UC3F) EEPROM
Blocks of the UC3F EEPROM that are protected (PROTECT[M] = 1, SBEN[N] = 1 and SBPROTECT[N]
= 1) will not be programmed. Also, if EPEE = 0, no programming voltages will be applied to the array. If
B0EPEE = 0, no programming voltages will be applied to block 0 or small block 0 depending on the state
of SBEN[0] and the configuration of the array.
21.3.7.1
The UC3F EEPROM module requires a sequence of writes to the high voltage control register
(UC3FCTL) and to the program data latch in order to enable the high voltage to the array or shadow
information for program operation. The required hardware program sequence follows.
21-22
1. Write PROTECT[0:7] and SBPROTECT[0:1] to disable protection on blocks to be programmed.
2. Write BLOCK[0:7] and SBBLOCK[0:1] to select the array blocks to be programmed, SES = 1 and
3. Programming write — A successful write to the array location to be programmed. This write
4. Write EHV = 1 in the UC3FCTL register.
5. Read the UC3FCTL register until HVS = 0.
6. Read the UC3FCTL, confirm PEGOOD = 1.
PE = 0 in the UC3FCTL register.
updates the program data latch with the information to be programmed. In addition, the addressof
the first programming write is latched in the UC3F memory interface block. All accesses of the
array after the first write are to the same address regardless of the address provided. Thus the
locations accessed after the first programming write are limited to the location to be programmed.
The last write to the program data latch is saved for programming.
Program Sequence
BLOCK[0:7] and SBBLOCK[0:1] in conjunction with SBEN[0:1]
determine which blocks/small blocks in the array are enabled for
programming operation. Just because a BLOCK or SBBLOCK bit is
enabled (set to 1), no programming can occur in the corresponding
block/small block unless the programming operation specifically targets an
address location within that block/small block to program. If BLOCK or
SBBLOCK is not set to 1, no address locations in that corresponding block
or small block can be programmed.
If a byte of the program data latch has not received a programming write, no
programming voltages will be applied to the corresponding byte in the array.
Once EHV has been set, writes to the program data latch are disabled until
EHV is cleared to 0.
The values of the EPEE and B0EPEE inputs are latched with the assertion
of EHV to determine the array protection state for the program operation. It
is assumed that the EPEE and B0EPEE inputs are setup prior to the assertion
of EHV.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
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Freescale Semiconductor