MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 355

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

1. For an illustration of device connections on the data bus, see
9.5.3
Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories while the
MPC561/MPC563 data bus pads are optimized to 2.6-V memories, and cannot tolerate more than 3.1 V.
When connecting 3.3-V devices to the E-bus, and performing read and write operations, this mode should
be invoked in order to avoid long term reliability issues of the data pads.
When the PDMCR2[PREDIS_EN] bit is set, the MPC561/MPC563 will discharge the bus during the
address phase of any write cycle prior to the data phase. The data bus will be discharged from up to 5 V to
a level which is suitable to the low voltage drivers. In most cases, the ORx[EHTR] bit of the relevant
memory bank, should be set along with the PREDIS_EN bit in order to reserve sufficient time for the
Freescale Semiconductor
CLKOUT
BR
BG
BB
ADDR[0:1]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
STS
Data
TA
1
Data Bus Pre-Discharge Mode
Figure 9-10. Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size
MPC561/MPC563 Reference Manual, Rev. 1.2
ADDR
00
ABCDEFGH
Figure
9-23.
10
ADDR + 2
EFGHEFGH
External Bus Interface
9-15